The influence of PMOSFET gate length on the parameter degradation relations under negative bias temperature insta- bility （NBTI） stress is studied. The threshold voltage degradation increases with reducing the gate ...The influence of PMOSFET gate length on the parameter degradation relations under negative bias temperature insta- bility （NBTI） stress is studied. The threshold voltage degradation increases with reducing the gate length. By calculating the relations between the threshold voltage and the linear/saturation drain current, we obtain their correlation coefficients. Comparing the test result with the calculated linear/saturation current value, we obtain the ratio factors. The ratio factors decrease differently when the gate length diminishes. When the gate length reduces to some degree, the linear ratio factor decreases from greater than 1 to nearly 1, but the saturation factor decreases from greater than l to smaller than 1. This results from the influence of mobility and the velocity saturation effect. Moreover, due to the un-uniform distribution of potential damages along the channel, the descending slopes of the curve are different.展开更多
The effects of gate length L_G on breakdown voltage VBRare investigated in AlGaN/GaN high-electron-mobility transistors（HEMTs） with L_G= 1 μm^20 μm. With the increase of L_G, VBRis first increased, and then satura...The effects of gate length L_G on breakdown voltage VBRare investigated in AlGaN/GaN high-electron-mobility transistors（HEMTs） with L_G= 1 μm^20 μm. With the increase of L_G, VBRis first increased, and then saturated at LG= 3 μm. For the HEMT with L_G= 1 μm, breakdown voltage VBRis 117 V, and it can be enhanced to 148 V for the HEMT with L-_G= 3 μm. The gate length of 3 μm can alleviate the buffer-leakage-induced impact ionization compared with the gate length of 1 μm, and the suppression of the impact ionization is the reason for improving the breakdown voltage.A similar suppression of the impact ionization exists in the HEMTs with LG〉 3 μm. As a result, there is no obvious difference in breakdown voltage among the HEMTs with LG= 3 μm^20 μm, and their breakdown voltages are in a range of 140 V–156 V.展开更多
Subject Code:F01With the support by the National Natural Science Foundation of China,the research team led by Prof.Peng Lianmao(彭练矛)and Prof.Zhang Zhiyong(张志勇)at the Key Laboratory for the Physics and Chemistry ...Subject Code:F01With the support by the National Natural Science Foundation of China,the research team led by Prof.Peng Lianmao(彭练矛)and Prof.Zhang Zhiyong(张志勇)at the Key Laboratory for the Physics and Chemistry of Nanodevices and Department of Electronics,Peking University,Beijing,recently reported that carbon nanotube CMOS FETs were scaled down to the 5nm gate length and presented展开更多
A design of a high-speed multi-core processor with compact size is a trending approach in the Integrated Circuits(ICs)fabrication industries.Because whenever device size comes down into narrow,designers facing many po...A design of a high-speed multi-core processor with compact size is a trending approach in the Integrated Circuits(ICs)fabrication industries.Because whenever device size comes down into narrow,designers facing many power den-sity issues should be reduced by scaling threshold voltage and supply voltage.Initially,Complementary Metal Oxide Semiconductor(CMOS)technology sup-ports power saving up to 32 nm gate length,but further scaling causes short severe channel effects such as threshold voltage swing,mobility degradation,and more leakage power(less than 32)at gate length.Hence,it directly affects the arithmetic logic unit(ALU),which suffers a significant power density of the scaled multi-core architecture.Therefore,it losses reliability features to get overheating and increased temperature.This paper presents a novel power mini-mization technique for active 4-bit ALU operations using Fin Field Effect Tran-sistor(FinFET)at 22 nm technology.Based on this,a diode is directly connected to the load transistor,and it is active only at the saturation region as a function.Thereby,the access transistor can cutoff of the leakage current,and sleep transis-tors control theflow of leakage current corresponding to each instant ALU opera-tion.The combination of transistors(access and sleep)reduces the leakage current from micro to nano-ampere.Further,the power minimization is achieved by con-necting the number of transistors(6T and 10T)of the FinFET structure to ALU with 22 nm technology.For simulation concerns,a Tanner(T-Spice)with 22 nm technology implements the proposed design,which reduces threshold vol-tage swing,supply power,leakage current,gate length delay,etc.As a result,it is quite suitable for the ALU architecture of a high-speed multi-core processor.展开更多
Silicon on insulator (SOI) technology permits a good solution to the miniaturization as the MOSFET size scales down. This paper is about to compare the electrical performance of nanoscale FD-SOI MOSFET at various gate...Silicon on insulator (SOI) technology permits a good solution to the miniaturization as the MOSFET size scales down. This paper is about to compare the electrical performance of nanoscale FD-SOI MOSFET at various gate lengths. The performance is compared and contrasted with the help of threshold voltage, subthreshold slope, on-state current and leakage current. Interestingly, by decreasing the gate length, the leakage current and on-state current are increased but the threshold voltage is decreased and the sub-threshold slope is degraded. Silvaco two-dimensional simulations are used to analyze the performance of the proposed structures.展开更多
基金supported by the National Basic Research Program of China(Grant No.2011CBA00606)the National Natural Science Foundation of China(Grant Nos.61334002,61106106,and 61176130)the Fundamental Research Fund for the Central Universities of China(Grant No.JB140415)
文摘The influence of PMOSFET gate length on the parameter degradation relations under negative bias temperature insta- bility （NBTI） stress is studied. The threshold voltage degradation increases with reducing the gate length. By calculating the relations between the threshold voltage and the linear/saturation drain current, we obtain their correlation coefficients. Comparing the test result with the calculated linear/saturation current value, we obtain the ratio factors. The ratio factors decrease differently when the gate length diminishes. When the gate length reduces to some degree, the linear ratio factor decreases from greater than 1 to nearly 1, but the saturation factor decreases from greater than l to smaller than 1. This results from the influence of mobility and the velocity saturation effect. Moreover, due to the un-uniform distribution of potential damages along the channel, the descending slopes of the curve are different.
基金Project supported by the National Natural Science Foundation of China(Grant Nos.61334002,61106106,and 61204085)
文摘The effects of gate length L_G on breakdown voltage VBRare investigated in AlGaN/GaN high-electron-mobility transistors（HEMTs） with L_G= 1 μm^20 μm. With the increase of L_G, VBRis first increased, and then saturated at LG= 3 μm. For the HEMT with L_G= 1 μm, breakdown voltage VBRis 117 V, and it can be enhanced to 148 V for the HEMT with L-_G= 3 μm. The gate length of 3 μm can alleviate the buffer-leakage-induced impact ionization compared with the gate length of 1 μm, and the suppression of the impact ionization is the reason for improving the breakdown voltage.A similar suppression of the impact ionization exists in the HEMTs with LG〉 3 μm. As a result, there is no obvious difference in breakdown voltage among the HEMTs with LG= 3 μm^20 μm, and their breakdown voltages are in a range of 140 V–156 V.
文摘Subject Code:F01With the support by the National Natural Science Foundation of China,the research team led by Prof.Peng Lianmao(彭练矛)and Prof.Zhang Zhiyong(张志勇)at the Key Laboratory for the Physics and Chemistry of Nanodevices and Department of Electronics,Peking University,Beijing,recently reported that carbon nanotube CMOS FETs were scaled down to the 5nm gate length and presented
文摘A design of a high-speed multi-core processor with compact size is a trending approach in the Integrated Circuits(ICs)fabrication industries.Because whenever device size comes down into narrow,designers facing many power den-sity issues should be reduced by scaling threshold voltage and supply voltage.Initially,Complementary Metal Oxide Semiconductor(CMOS)technology sup-ports power saving up to 32 nm gate length,but further scaling causes short severe channel effects such as threshold voltage swing,mobility degradation,and more leakage power(less than 32)at gate length.Hence,it directly affects the arithmetic logic unit(ALU),which suffers a significant power density of the scaled multi-core architecture.Therefore,it losses reliability features to get overheating and increased temperature.This paper presents a novel power mini-mization technique for active 4-bit ALU operations using Fin Field Effect Tran-sistor(FinFET)at 22 nm technology.Based on this,a diode is directly connected to the load transistor,and it is active only at the saturation region as a function.Thereby,the access transistor can cutoff of the leakage current,and sleep transis-tors control theflow of leakage current corresponding to each instant ALU opera-tion.The combination of transistors(access and sleep)reduces the leakage current from micro to nano-ampere.Further,the power minimization is achieved by con-necting the number of transistors(6T and 10T)of the FinFET structure to ALU with 22 nm technology.For simulation concerns,a Tanner(T-Spice)with 22 nm technology implements the proposed design,which reduces threshold vol-tage swing,supply power,leakage current,gate length delay,etc.As a result,it is quite suitable for the ALU architecture of a high-speed multi-core processor.
文摘Silicon on insulator (SOI) technology permits a good solution to the miniaturization as the MOSFET size scales down. This paper is about to compare the electrical performance of nanoscale FD-SOI MOSFET at various gate lengths. The performance is compared and contrasted with the help of threshold voltage, subthreshold slope, on-state current and leakage current. Interestingly, by decreasing the gate length, the leakage current and on-state current are increased but the threshold voltage is decreased and the sub-threshold slope is degraded. Silvaco two-dimensional simulations are used to analyze the performance of the proposed structures.
