Substrate Hot Holes Injection Induced Breakdown Characteristics of Thin Gate Oxides

A substrate hot holes injection method is used to quantitatively examine the roles of electrons and holes separately in thin gate oxides breakdown.The shift of threshold voltage under different stress is discussed.It is indicated that positive charges are trapped in SiO 2 while hot electrons are necessary for SiO 2 breakdown.The anode holes injection model and the electron traps generation model is linked into a consistent model,describing the oxide wearout as an electron correlated holes trap creation process.The results show that the limiting factor in thin gate oxides breakdown depends on the balance between the amount of injected hot electrons and holes.The gate oxides breakdown is a two step process.The first step is hot electron's breaking Si-O bonds and producing some dangling bonds to be holes traps.Then the holes are trapped and a conducted path is produced in the oxides.The joint effect of hot electrons and holes makes the thin gate oxides breakdown complete.

Low switching loss and increased short-circuit capability split-gate SiC trench MOSFET with p-type pillar

A split-gate SiC trench gate MOSFET with stepped thick oxide, source-connected split-gate(SG), and p-type pillar(ppillar) surrounded thick oxide shielding region(GSDP-TMOS) is investigated by Silvaco TCAD simulations. The sourceconnected SG region and p-pillar shielding region are introduced to form an effective two-level shielding, which reduces the specific gate–drain charge(Q_(gd,sp)) and the saturation current, thus reducing the switching loss and increasing the short-circuit capability. The thick oxide that surrounds a p-pillar shielding region efficiently protects gate oxide from being damaged by peaked electric field, thereby increasing the breakdown voltage(BV). Additionally, because of the high concentration in the n-type drift region, the electrons diffuse rapidly and the specific on-resistance(Ron,sp) becomes smaller.In the end, comparing with the bottom p~+ shielded trench MOSFET(GP-TMOS), the Baliga figure of merit(BFOM,BV~2/R_(on,sp)) is increased by 169.6%, and the high-frequency figure of merit(HF-FOM, R_(on,sp) × Q_(gd,sp)) is improved by310%, respectively.

Investigation of degradation and recovery characteristics of NBTI in 28-nm high-k metal gate process

Degradation induced by the negative bias temperature instability(NBTI)can be attributed to three mutually uncoupled physical mechanisms,i.e.,the generation of interface traps(ΔV_(IT)),hole trapping in pre-existing gate oxide defects(ΔV_(HT)),and the generation of gate oxide defects(ΔV_(OT)).In this work,the characteristic of NBTI for p-type MOSFET fabricated by using a 28-nm high-k metal gate(HKMG)process is thoroughly studied.The experimental results show that the degradation is enhanced at a larger stress bias and higher temperature.The effects of the three underlying subcomponents are evaluated by using the comprehensive models.It is found that the generation of interface traps dominates the NBTI degradation during long-time NBTI stress.Moreover,the NBTI parameters of the power-law time exponent and temperature activation energy as well as the gate oxide field acceleration are extracted.The dependence of operating lifetime on stress bias and temperature is also discussed.It is observed that NBTI lifetime significantly decreases as the stress increases.Furthermore,the decrease of charges related to interface traps and hole detrapping in pre-existing gate oxide defects are used to explain the recovery mechanism after stress.

Breakdown Voltage and Charge to Breakdown Investigation of Gate Oxide of 0.18μm Dual Gate CMOS Process with Different Measurement Methods

Breakdown voltage （Vbd） and charge to breakdown （Qbd） are two parameters often used to evaluate gate oxide reliability. In this paper,we investigate the effects of measurement methods on Vbd and Qbd of the gate oxide of a 0.18μm dual gate CMOS process. Voltage ramps （V-ramp） and current ramps （J-ramp） are used to evaluate gate oxide reliability. The thin and thick gate oxides are all evaluated in the accumulation condition. Our experimental results show that the measurement methods affect Vbd only slightly but affect Qbd seriously,as do the measurement conditions.This affects the I-t curves obtained with the J-ramp and V-ramp methods. From the I-t curve,it can be seen that Qbd obtained using a J-ramp is much bigger than that with a V-ramp. At the same time, the Weibull slopes of Qbd are definitely smaller than those of Vbd. This means that Vbd is more reliable than Qbd, Thus we should be careful to use Qbd to evaluate the reliability of 0.18μm or beyond CMOS process gate oxide.

Analysis of hot-carrier degradation in N-LDMOS transistor with step gate oxide

In order to minimize the hot-carrier effect（HCE）and maintain on-state performance in the high voltage N-type lateral double diffused MOS（N-LDMOS）, an optimized device structure with step gate oxide is proposed. Compared with the conventional configuration, the electric field under the gate along the Si-SiO2 interface in the presented N-LDMOS can be greatly reduced, which favors reducing the hot-carrier degradation. The step gate oxide can be achieved by double gate oxide growth, which is commonly used in some smart power ICs. The differences in hot-carrier degradations between the novel structure and the conventional structure are investigated and analyzed by 2D technology computer-aided design（TCAD）numerical simulations, and the optimal length of the thick gate oxide part in the novel N-LDMOS device can also be acquired on the basis of maintaining the characteristic parameters of the conventional device. Finally, the practical degradation measurements of some characteristic parameters can also be carried out. It is found that the hot-carrier degradation of the novel N-LDMOS device can be improved greatly.

SILC Mechanism in Degraded Gate Oxide of Different Thickness

It is shown that traps are generated asymmetrically in the thin gate oxides with different thickness during high field degradation,as well as the multi-mechanism plays role in the Stress Induced Leakage Current (SILC).These factors perform differently in gate oxide of different thickness.A comparison is drew between several analyzing models.Trap assisted tunneling is preferred for thinner samples,while Pool-Frankel like mechanism or thermal emission mechanism should apply to the thick ones.

Effect of Metal Contamination on Characteristics of Ultra-Thin Gate Oxide

The purpose of this work relates to study on the characteristics of ultra thin gate oxide (2 5nm thickness) and the effect of metal Al,Zr,and Ta contamination on GOI.The controlled metallic contamination experiments are carried out by depositing a few ppm contaminated metal and low pH solutions on the wafers.The maximum metal surface concentration is controlled at about 10 12 cm -2 level in order to simulate metal contamination during ultra clean processing.A ramped current stress for intrinsic charge to breakdown measurements with gate injection mode is used to examine the characteristics of these ultra thin gate oxides and the effect of metal contamination on GOI.It is the first time to investigate the influence of metal Zr and Ta contamination on 2 5nm ultra thin gate oxide.It is demonstrated that there is little effect of Al contamination on GOI,while Zr contamination is the most detrimental to GOI,and early breakdown has happened to wafers contaminated by Ta.

High performance trench MOS barrier Schottky diode with high-k gate oxide

A novel trench MOS barrier Schottky diode（TMBS） device with a high-k material introduced into the gate insulator is reported, which is named high-k TMBS. By simulation with Medici, it is found that the high-k TMBS can have 19.8% lower leakage current while maintaining the same breakdown voltage and forward turn-on voltage compared with the conventional regular trench TMBS.

The conduction mechanism of stress induced leakage current through ultra-thin gate oxide under constant voltage stresses

The conduction mechanism of stress induced leakage current （SILC） through 2nm gate oxide is studied over a gate voltage range between 1.7V and stress voltage under constant voltage stress （CVS）. The simulation results show that the SILC is formed by trap-assisted tunnelling （TAT） process which is dominated by oxide traps induced by high field stresses. Their energy levels obtained by this work are approximately 1.9eV from the oxide conduction band, and the traps are believed to be the oxygen-related donor-like defects induced by high field stresses. The dependence of the trap density on stress time and oxide electric field is also investigated.

Impact of STI indium implantation on reliability of gate oxide

The impacts of shallow trench isolation(STI)indium implantation on gate oxide and device characteristics are studied in this work.The stress modulation effect is confirmed in this research work.An enhanced gate oxide oxidation rate is observed due to the enhanced tensile stress,and the thickness gap is around 5%.Wafers with and without STI indium implantation are manufactured using the 150-nm silicon on insulator(SOI)process.The ramped voltage stress and time to breakdown capability of the gate oxide are researched.No early failure is observed for both wafers the first time the voltage is ramped up.However,a time dependent dielectric breakdown(TDDB)test shows more obvious evidence that the gate oxide quality is weakened by the STI indium implantation.Meanwhile,the device characteristics are compared,and the difference between two devices is consistent with the equivalent oxide thickness(EOT)gap.

Gate leakage current of NMOSFET with ultra-thin gate oxide

As dimensions of the metal-oxide-semiconductor field-effect transistor (MOSFET) are scaling down and the thickness of gate oxide is decreased,the gate leakage becomes more and more prominent and has been one of the most important limiting factors to MOSFET and circuits lifetime.Based on reliability theory and experiments,the direct tunneling current in lightly-doped drain (LDD) NMOSFET with 1.4 nm gate oxide fabricated by 90 nm complementary metal oxide semiconductor (CMOS) process was studied in depth.High-precision semiconductor parameter analyzer was used to conduct the tests.Law of variation of the direct tunneling (DT) current with channel length,channel width,measuring voltage,drain bias and reverse substrate bias was revealed.The results show that the change of the DT current obeys index law;there is a linear relationship between gate current and channel dimension;drain bias and substrate bias can reduce the gate current.

Low-Frequency Noise in Amorphous Indium Zinc Oxide Thin Film Transistors with Aluminum Oxide Gate Insulator

Low-frequency noise（LFN） in all operation regions of amorphous indium zinc oxide（a-IZO） thin film transistors（TFTs） with an aluminum oxide gate insulator is investigated. Based on the LFN measured results, we extract the distribution of localized states in the band gap and the spatial distribution of border traps in the gate dielectric,and study the dependence of measured noise on the characteristic temperature of localized states for a-IZO TFTs with Al2 O3 gate dielectric. Further study on the LFN measured results shows that the gate voltage dependent noise data closely obey the mobility fluctuation model, and the average Hooge＇s parameter is about 1.18×10^-3.Considering the relationship between the free carrier number and the field effect mobility, we simulate the LFN using the △N-△μ model, and the total trap density near the IZO/oxide interface is about 1.23×10^18 cm^-3eV^-1.

On-Resistance Degradations Under Different Stress Conditions in High Voltage pLEDMOS Transistors and an Improved Method

The on-resistance degradations of the p-type lateral extended drain MOS transistor （pLEDMOS） with thick gate oxide under different hot carrier stress conditions are different, which has been experimentally investigated. This difference results from the interface trap generation and the hot electron injection, and trapping into the thick gate oxide and field oxide of the pLEDMOS transistor. An improved method to reduce the on-resistance degradations is also presented, which uses the field oxide as the gate oxide instead of the thick gate oxide. The effects are analyzed with a MEDICI simulator.

High Performance 70nm CMOS Devices

A high performance 70nm CMOS device has been demonstrated for the first time in the continent, China. Some innovations in techniques are applied to restrain the short channel effect and improve the driving ability, such as 3nm nitrided oxide, dual poly Si gate electrode, novel super steep retrograde channel doping by heavy ion implantation, ultra shallow S/D extension formed by Ge PAI(Pre Amorphism Implantation) plus LEI(Low Energy Implantation), thin and low resistance Ti SALICIDE by Ge PAI and special cleaning, etc. The shortest channel length of the CMOS device is 70nm. The threshold voltages, G m and off current are 0 28V,490mS·mm -1 and 0 08nA/μm for NMOS and -0 3V,340mS·mm -1 and 0 2nA/μm for PMOS, respectively. Delays of 23 5ps/stage at 1 5V, 17 5ps/stage at 2 0V and 12 5ps/stage at 3V are achieved in the 57 stage unloaded 100nm CMOS ring oscillator circuits.

Polysilicon Over-Etching Time Control of Advanced CMOS Processing with Emission Microscopy

The emission microscopy （EMMI） test is proposed as an effective method to control the polysilicon over-etching time of advanced CMOS processing combined with a novel test structure, named a poly-edge structure. From the values of the breakdown voltage （Vbd） of MOS capacitors （poly-edge structure） ,it was observed that,with for the initial polysilicon etching-time, almost all capacitors in one wafer failed under the initial failure model. With the increase of polysilicon over-etching time, the number of the initial failure capacitors decreased. Finally, no initial failure capacitors were observed after the polysilicon over-etching time was increased by 30s. The breakdown samples with the initial failure model and intrinsic failure model underwent EMMI tests. The EMMI test results show that the initial failure of capacitors with poly-edge structures was due to the bridging effect between the silicon substrate and the polysilicon gate caused by the residual polysilicon in the ditch between the shallow-trench isolation region and the active area, which will short the polysilicon gate with silicon substrate after the silicide process.

Experimental Evidence of Interface-Trap-Related SILC in Ultrathin (4nm- and 2.5nm-Thick) n-MOSFET and p-MOSFET Under Hot-Carrier Stress

Stress-induced leakage current (SILC) of ultrathin gate oxide is investigated by observing the generation of interface traps for n-MOSFET and p-MOSFET under hot-carrier stress.It is found experimentally that there is linear correlation between the generation of interface traps and SILC for both types of MOSFET with different channel lengths (including 1,0.5,0.275,and 0.135μm) and different gate oxide thickness (4nm and 2.5nm).These experimental evidences show that the SILC has a strong dependence on interface traps.

An Improved Method to Extract Generation of Interface Trap in Hot-Carrier-Stressed LDD n-MOSFET

A new improved technique,based on the direct current current voltage and charge pumping methods,is proposed for measurements of interface traps density in the channel and the drain region for LDD n MOSFET.This technique can be applied to virgin samples and those subjected to hot carrier stress,and the latter are known to cause the interface damage in the drain region and the channel region.The generation of interface traps density in the channel region and in the drain region can be clearly distinguished by using this technique.

Enhancement-mode InAlN/GaN MISHEMT with low gate leakage current

We report an enhancement-mode InAlN/GaN MISHEMT with a low gate leakage current by a thermal oxidation technique under gate.The off-state source-drain current density is as low as～10^（17） A/mm at V_（GS）= 0 V and V_（DS） = 5 V.The threshold voltage is measured to be ＋0.8 V by linear extrapolation from the transfer characteristics.The E-mode device exhibits a peak transconductance of 179 mS/mm at a gate bias of 3.4 V.A low reverse gate leakage current density of 4.9×10^（17） A/mm is measured at V_（GS） =-15 V.

Body-contact self-bias effect in partially depleted SOI-CMOS and alternatives to suppress floating body effect

As SOI-CMOS technology nodes reach the tens ofnanometer regime, body-contacts become more and more ineffective to suppress the floating body effect. In this paper, self-bias effect as the cause for this failure is analyzed and discussed in depth with respect to different structures and conditions. Other alternative approaches to suppressing the floating body effect are also introduced and discussed.