A set of 100-nm gate-length In P-based high electron mobility transistors(HEMTs)were designed and fabricated with different gate offsets in gate recess.A novel technology was proposed for independent definition of gat...A set of 100-nm gate-length In P-based high electron mobility transistors(HEMTs)were designed and fabricated with different gate offsets in gate recess.A novel technology was proposed for independent definition of gate recess and T-shaped gate by electron beam lithography.DC and RF measurement was conducted.With the gate offset varying from drain side to source side,the maximum drain current(I_(ds,max))and transconductance(g_(m,max))increased.In the meantime,fTdecreased while f;increased,and the highest fmax of 1096 GHz was obtained.It can be explained by the increase of gate-source capacitance and the decrease of gate-drain capacitance and source resistance.Output conductance was also suppressed by gate offset toward source side.This provides simple and flexible device parameter selection for HEMTs of different usages.展开更多
In this paper, in order to solve the interface-trap issue and enhance the transconductance induced by high-k dielectric in metal-insulator-semiconductor （MIS） high electron mobility transistors （HEMTs）, we demonst...In this paper, in order to solve the interface-trap issue and enhance the transconductance induced by high-k dielectric in metal-insulator-semiconductor （MIS） high electron mobility transistors （HEMTs）, we demonstrate better performances of recessed-gate A1203 MIS-HEMTs which are fabricated by Fluorine-based Si3N4 etching and chlorine- based A1CaN etching with three etching times （15 s, 17 s and 19 s）. The gate leakage current of MIS-HEMT is about three orders of magnitude lower than that of A1GaN/CaN HEMT. Through the recessed-gate etching, the transconductanee increases effectively. When the recessed-gate depth is 1.02 nm, the best interface performance with Tit----（0.20--1.59） p^s and Dit ：（0.55-1.08）x 1012 cm-2.eV- 1 can be obtained. After chlorine-based etching, the interface trap density reduces considerably without generating any new type of trap. The accumulated chlorine ions and the N vacancies in the AIGaN surface caused by the plasma etching can degrade the breakdown and the high frequency performances of devices. By comparing the characteristics of recessed-gate MIS-HEMTs with different etching times, it is found that a low power chlorine-based plasma etching for a short time （15 s in this paper） can enhance the performances of MIS-HEMTs effectively.展开更多
AlGaN/GaN HEMTs with 0.2μm V-gate recesses were developed.The 0.2μm recess lengths were shrunk from the 0.6μm designed gate footprint length after isotropic SiN deposition and anisotropic recessed gate dry etching....AlGaN/GaN HEMTs with 0.2μm V-gate recesses were developed.The 0.2μm recess lengths were shrunk from the 0.6μm designed gate footprint length after isotropic SiN deposition and anisotropic recessed gate dry etching.The AlGaN/GaN HEMTs with 0.2μm V-gate recesses on sapphire substrates exhibited a current gain cutoff frequency f_t of 35 GHz and a maximum frequency of oscillation f_（max） of 60 GHz.At 10 GHz frequency and 20 V drain bias,the V-gate recess devices exhibited an output power density of 4.44 W/mm with the associated power added efficiency as high as 49%.展开更多
We fabricated 88 nm gate-length InP-based InAlAs/InGaAs high electron mobility transistors（HEMTs） with a current gain cutoff frequency of 100 GHz and a maximum oscillation frequency of 185 GHz.The characteristics of...We fabricated 88 nm gate-length InP-based InAlAs/InGaAs high electron mobility transistors（HEMTs） with a current gain cutoff frequency of 100 GHz and a maximum oscillation frequency of 185 GHz.The characteristics of HEMTs with side-etched region lengths（L_（Side）） of 300,412 and 1070 nm were analyzed.With the increase in L_（Side）,the kink effect became notable in the DC characteristics,which resulted from the surface state and the effect of impact ionization.The kink effect was qualitatively explained through energy band diagrams,and then eased off by reducing the L_（Side）.Meanwhile,the L_（Side） dependence of the radio frequency characteristics,which were influenced by the parasitic capacitance,as well as the parasitic resistance of the source and drain,was studied.This work will be of great importance in fabricating high-performance InP HEMTs.展开更多
In this work, AlGaN/GaN FinFETs with different fin widths have been successfully fabricated, and the recessed-gate FinFETs are fabricated for comparison. The recessed-gate FinFETs exhibit higher transconductance value...In this work, AlGaN/GaN FinFETs with different fin widths have been successfully fabricated, and the recessed-gate FinFETs are fabricated for comparison. The recessed-gate FinFETs exhibit higher transconductance value and positive shift of threshold voltage. Moreover, with the fin width of the recessed-gate FinFETs increasing, the variations of both threshold voltage and the transconductance increase. Next, transfer characteristics of the recessed-gate FinFETs with different fin widths and recessed-gate depths are simulated by Silvaco software. The relationship between the threshold voltage and the AlGaN layer thickness has been investigated. The simulation results indicate that the slope of threshold voltage variation reduces with the fin width decreasing. Finally, a simplified threshold voltage model for recessed-gate FinFET is established,which agrees with both the experimental results and simulation results.展开更多
InA1As/InGaAs high electron mobility transistors （HEMTs） on an InP substrate with well-balanced cutoff frequency fT and maximum oscillation frequency frnax are reported. An InA1As/InGaAs HEMT with 100-nm gate length...InA1As/InGaAs high electron mobility transistors （HEMTs） on an InP substrate with well-balanced cutoff frequency fT and maximum oscillation frequency frnax are reported. An InA1As/InGaAs HEMT with 100-nm gate length and gate width of 2 × 50 μm shows excellent DC characteristics, including full channel current of 724 mA/mm, extrinsic maximum transconductance gm.max of 1051 mS/mm, and drain-gate breakdown voltage BVDG of 5.92 V. In addition, this device exhibits fT = 249 GHz and fmax = 415 GHz. These results were obtained by fabricating an asymmetrically recessed gate and minimizing the parasitic resistances. The specific Ohmic contact resistance was reduced to 0.031 0.mm. Moreover, the fT obtained in this work is the highest ever reported in 100-nm gate length InA1As/InGaAs InP-based HEMTs. The outstanding gm.max, fT, fmax, and good BVDG make the device suitable for applications in low noise amplifiers, power amplifiers, and high speed circuits.展开更多
In this paper, a surface potential based threshold voltage model of fully-depleted（FD） recessed-source/drain（Re-S/D）silicon-on-insulator（SOI） metal-oxide semiconductor field-effect transistor（MOSFET） is presen...In this paper, a surface potential based threshold voltage model of fully-depleted（FD） recessed-source/drain（Re-S/D）silicon-on-insulator（SOI） metal-oxide semiconductor field-effect transistor（MOSFET） is presented while considering the effects of high-k gate-dielectric material induced fringing-field. The two-dimensional（2D） Poisson＇s equation is solved in a channel region in order to obtain the surface potential under the assumption of the parabolic potential profile in the transverse direction of the channel with appropriate boundary conditions. The accuracy of the model is verified by comparing the model＇s results with the 2D simulation results from ATLAS over a wide range of channel lengths and other parameters,including the dielectric constant of gate-dielectric material.展开更多
基金Project supported by the National Nature Science Foundation of China(Grant No.61434006)。
文摘A set of 100-nm gate-length In P-based high electron mobility transistors(HEMTs)were designed and fabricated with different gate offsets in gate recess.A novel technology was proposed for independent definition of gate recess and T-shaped gate by electron beam lithography.DC and RF measurement was conducted.With the gate offset varying from drain side to source side,the maximum drain current(I_(ds,max))and transconductance(g_(m,max))increased.In the meantime,fTdecreased while f;increased,and the highest fmax of 1096 GHz was obtained.It can be explained by the increase of gate-source capacitance and the decrease of gate-drain capacitance and source resistance.Output conductance was also suppressed by gate offset toward source side.This provides simple and flexible device parameter selection for HEMTs of different usages.
基金supported by the National Key Science and Technology Special Project,China (Grant No. 2008ZX01002-002)the National Natural Science Foundation of China (Grant No. 60736033)
文摘In this paper, in order to solve the interface-trap issue and enhance the transconductance induced by high-k dielectric in metal-insulator-semiconductor （MIS） high electron mobility transistors （HEMTs）, we demonstrate better performances of recessed-gate A1203 MIS-HEMTs which are fabricated by Fluorine-based Si3N4 etching and chlorine- based A1CaN etching with three etching times （15 s, 17 s and 19 s）. The gate leakage current of MIS-HEMT is about three orders of magnitude lower than that of A1GaN/CaN HEMT. Through the recessed-gate etching, the transconductanee increases effectively. When the recessed-gate depth is 1.02 nm, the best interface performance with Tit----（0.20--1.59） p^s and Dit ：（0.55-1.08）x 1012 cm-2.eV- 1 can be obtained. After chlorine-based etching, the interface trap density reduces considerably without generating any new type of trap. The accumulated chlorine ions and the N vacancies in the AIGaN surface caused by the plasma etching can degrade the breakdown and the high frequency performances of devices. By comparing the characteristics of recessed-gate MIS-HEMTs with different etching times, it is found that a low power chlorine-based plasma etching for a short time （15 s in this paper） can enhance the performances of MIS-HEMTs effectively.
基金Project supported by the National Key Science & Technology Special Project,China(No.2008ZX01002-002)the Major Program and State Key Program of National Natural Science Foundation of China(Nos.60890191,60736033)the Fundamental Research Funds for the Central Universities,China(Nos.K50510250003,K50510250006)
文摘AlGaN/GaN HEMTs with 0.2μm V-gate recesses were developed.The 0.2μm recess lengths were shrunk from the 0.6μm designed gate footprint length after isotropic SiN deposition and anisotropic recessed gate dry etching.The AlGaN/GaN HEMTs with 0.2μm V-gate recesses on sapphire substrates exhibited a current gain cutoff frequency f_t of 35 GHz and a maximum frequency of oscillation f_（max） of 60 GHz.At 10 GHz frequency and 20 V drain bias,the V-gate recess devices exhibited an output power density of 4.44 W/mm with the associated power added efficiency as high as 49%.
基金Project supported by the National Basic Research Program of China(No.2010CB327502)
文摘We fabricated 88 nm gate-length InP-based InAlAs/InGaAs high electron mobility transistors（HEMTs） with a current gain cutoff frequency of 100 GHz and a maximum oscillation frequency of 185 GHz.The characteristics of HEMTs with side-etched region lengths（L_（Side）） of 300,412 and 1070 nm were analyzed.With the increase in L_（Side）,the kink effect became notable in the DC characteristics,which resulted from the surface state and the effect of impact ionization.The kink effect was qualitatively explained through energy band diagrams,and then eased off by reducing the L_（Side）.Meanwhile,the L_（Side） dependence of the radio frequency characteristics,which were influenced by the parasitic capacitance,as well as the parasitic resistance of the source and drain,was studied.This work will be of great importance in fabricating high-performance InP HEMTs.
基金Project supported by the National Key Research and Development Program of China(Grant No.2016YFB0400 300)the National Natural Science Foundation of China(Grant Nos.61574110,61574112,and 61474091)
文摘In this work, AlGaN/GaN FinFETs with different fin widths have been successfully fabricated, and the recessed-gate FinFETs are fabricated for comparison. The recessed-gate FinFETs exhibit higher transconductance value and positive shift of threshold voltage. Moreover, with the fin width of the recessed-gate FinFETs increasing, the variations of both threshold voltage and the transconductance increase. Next, transfer characteristics of the recessed-gate FinFETs with different fin widths and recessed-gate depths are simulated by Silvaco software. The relationship between the threshold voltage and the AlGaN layer thickness has been investigated. The simulation results indicate that the slope of threshold voltage variation reduces with the fin width decreasing. Finally, a simplified threshold voltage model for recessed-gate FinFET is established,which agrees with both the experimental results and simulation results.
基金Project supported by the National Basic Research Program of China(Grant No.2010CB327502)
文摘InA1As/InGaAs high electron mobility transistors （HEMTs） on an InP substrate with well-balanced cutoff frequency fT and maximum oscillation frequency frnax are reported. An InA1As/InGaAs HEMT with 100-nm gate length and gate width of 2 × 50 μm shows excellent DC characteristics, including full channel current of 724 mA/mm, extrinsic maximum transconductance gm.max of 1051 mS/mm, and drain-gate breakdown voltage BVDG of 5.92 V. In addition, this device exhibits fT = 249 GHz and fmax = 415 GHz. These results were obtained by fabricating an asymmetrically recessed gate and minimizing the parasitic resistances. The specific Ohmic contact resistance was reduced to 0.031 0.mm. Moreover, the fT obtained in this work is the highest ever reported in 100-nm gate length InA1As/InGaAs InP-based HEMTs. The outstanding gm.max, fT, fmax, and good BVDG make the device suitable for applications in low noise amplifiers, power amplifiers, and high speed circuits.
基金supported by the Science and Engineering Research Board(SERB),Department of Science and Technology,Ministry of Human Resource and Development,Government of India under Young Scientist Research(Grant No.SB/FTP/ETA-415/2012)
文摘In this paper, a surface potential based threshold voltage model of fully-depleted（FD） recessed-source/drain（Re-S/D）silicon-on-insulator（SOI） metal-oxide semiconductor field-effect transistor（MOSFET） is presented while considering the effects of high-k gate-dielectric material induced fringing-field. The two-dimensional（2D） Poisson＇s equation is solved in a channel region in order to obtain the surface potential under the assumption of the parabolic potential profile in the transverse direction of the channel with appropriate boundary conditions. The accuracy of the model is verified by comparing the model＇s results with the 2D simulation results from ATLAS over a wide range of channel lengths and other parameters,including the dielectric constant of gate-dielectric material.
