Gate-grounded NMOS （GGNMOS） devices with different device dimensions and layout floorplans have been designed and fabricated in 0.13-μm silicide CMOS technology. The snapback characteristics of these GGN-MOS device...Gate-grounded NMOS （GGNMOS） devices with different device dimensions and layout floorplans have been designed and fabricated in 0.13-μm silicide CMOS technology. The snapback characteristics of these GGN-MOS devices are measured using the transmission line pulsing （TLP） measurement technique. The relationships between snapback parameters and layout parameters are shown and analyzed. A TCAD device simulator is used to explain these relationships. From these results, the circuit designer can predict the behavior of the GGNMOS devices under high ESD current stress, and design area-efficient ESD protection circuits to sustain the required ESD level. Optimized layout rules for ESD protection in 0.13-μm silicide CMOS technology are also presented.展开更多
针对低温多晶硅(low temperature poly-silicon,LTPS)和低温多晶氧化物(low temperature polycrystalline oxide,LTPO)工艺下的有机电致发光显示器(organic light emitting diode,OLED)电路设计时,驱动译码电路瞬态产生大电流引起的闩...针对低温多晶硅(low temperature poly-silicon,LTPS)和低温多晶氧化物(low temperature polycrystalline oxide,LTPO)工艺下的有机电致发光显示器(organic light emitting diode,OLED)电路设计时,驱动译码电路瞬态产生大电流引起的闩锁效应烧坏器问题,提出一种具有瞬态电流限制能力的全N增强型金属氧化物半导体(N-enhancement type metal oxide semiconductor,NMOS)场效应管的译码器电路设计方法。该方法基于树状网络进行译码和限流,利用支路简并方法进行逻辑化简,采用共源共栅结构中的输出阻抗限制译码瞬态过程的最大电流;在SMIC 180 nm CMOS工艺下完成设计,核心电路面积为470.69μm^(2)。2种不同输入条件下的仿真结果表明,采用格雷码对输入激励进行编码的5-32全NMOS译码器的功耗延迟积仅为9.77×10^(-20)J·s,比同等工艺、电源电压、温度条件下设计的CMOS 5-32译码器降低了81.8%;瞬态译码时的最大电流为11.69μA,比CMOS 5-32译码器降低了99.44%。展开更多
制播系统IP化发展过程中,SMPTE ST 2110协议规范并定义了制播系统中不同IP实体流的承载、同步和描述的标准,但只是解决了IP系统中传输层互联互通的问题,而NMOS(网络媒体开放规范)为SMPTE ST 2110的传输层规范补充了控制层与管理层,从而...制播系统IP化发展过程中,SMPTE ST 2110协议规范并定义了制播系统中不同IP实体流的承载、同步和描述的标准,但只是解决了IP系统中传输层互联互通的问题,而NMOS(网络媒体开放规范)为SMPTE ST 2110的传输层规范补充了控制层与管理层,从而将ST 2110本身复杂的操作抽象为提供接口以便于与任何控制系统交互的软件层,将本来复杂的底层操作变为简单的操作。本文主要介绍了制播系统中NMOS(网络媒体开放规范)实现方法,着重分析了IS-04(发现与注册)和IS-05(连接管理)实现细节。展开更多
基金supported by the National Natural Science Foundation of China(Nos.60773081,60777018)the AM Foundation by Science and Technology Commission of Shanghai Municipality(No.087009741000)the SDC Project by Science and Technology Commission of Shanghai Municipality(Nos.08706201800,077062008,08706201000)
文摘Gate-grounded NMOS （GGNMOS） devices with different device dimensions and layout floorplans have been designed and fabricated in 0.13-μm silicide CMOS technology. The snapback characteristics of these GGN-MOS devices are measured using the transmission line pulsing （TLP） measurement technique. The relationships between snapback parameters and layout parameters are shown and analyzed. A TCAD device simulator is used to explain these relationships. From these results, the circuit designer can predict the behavior of the GGNMOS devices under high ESD current stress, and design area-efficient ESD protection circuits to sustain the required ESD level. Optimized layout rules for ESD protection in 0.13-μm silicide CMOS technology are also presented.
文摘针对低温多晶硅(low temperature poly-silicon,LTPS)和低温多晶氧化物(low temperature polycrystalline oxide,LTPO)工艺下的有机电致发光显示器(organic light emitting diode,OLED)电路设计时,驱动译码电路瞬态产生大电流引起的闩锁效应烧坏器问题,提出一种具有瞬态电流限制能力的全N增强型金属氧化物半导体(N-enhancement type metal oxide semiconductor,NMOS)场效应管的译码器电路设计方法。该方法基于树状网络进行译码和限流,利用支路简并方法进行逻辑化简,采用共源共栅结构中的输出阻抗限制译码瞬态过程的最大电流;在SMIC 180 nm CMOS工艺下完成设计,核心电路面积为470.69μm^(2)。2种不同输入条件下的仿真结果表明,采用格雷码对输入激励进行编码的5-32全NMOS译码器的功耗延迟积仅为9.77×10^(-20)J·s,比同等工艺、电源电压、温度条件下设计的CMOS 5-32译码器降低了81.8%;瞬态译码时的最大电流为11.69μA,比CMOS 5-32译码器降低了99.44%。
文摘制播系统IP化发展过程中,SMPTE ST 2110协议规范并定义了制播系统中不同IP实体流的承载、同步和描述的标准,但只是解决了IP系统中传输层互联互通的问题,而NMOS(网络媒体开放规范)为SMPTE ST 2110的传输层规范补充了控制层与管理层,从而将ST 2110本身复杂的操作抽象为提供接口以便于与任何控制系统交互的软件层,将本来复杂的底层操作变为简单的操作。本文主要介绍了制播系统中NMOS(网络媒体开放规范)实现方法,着重分析了IS-04(发现与注册)和IS-05(连接管理)实现细节。
