The 45 K Onset Superconductivity and the Suppression of the Nematic Order in FeSe by Electrolyte Gating

The electronic doping effect on both the superconductivity and the nematic order in the FeSe nanoflake are investigated by using the electric-double-layer transistor configuration. The superconductivity can be effectively controlled by electronic doping, and the onset superconducting transition temperature Tc reaches as high as 45 K at a gate voltage Of Vg = 4 V. Meanwhile, the nematic phase is gradually suppressed with the increase of electronic doping （or Vg）. The results provide an effective method with variable charge doping for investigation of the rich physics in the FeSe superconductor.

Study on influences of TiN capping layer on time-dependent dielectric breakdown characteristic of ultra-thin EOT high-k metal gate NMOSFET with kMC TDDB simulations

The thickness effect of the TiN capping layer on the time dependent dielectric breakdown（TDDB） characteristic of ultra-thin EOT high-k metal gate NMOSFET is investigated in this paper.Based on experimental results,it is found that the device with a thicker TiN layer has a more promising reliability characteristic than that with a thinner TiN layer.From the charge pumping measurement and secondary ion mass spectroscopy（SIMS） analysis,it is indicated that the sample with the thicker TiN layer introduces more Cl passivation at the IL/Si interface and exhibits a lower interface trap density.In addition,the influences of interface and bulk trap density ratio Nit/Not are studied by TDDB simulations through combining percolation theory and the kinetic Monte Carlo（kMC） method.The lifetime reduction and Weibull slope lowering are explained by interface trap effects for TiN capping layers with different thicknesses.

Temperature- and voltage-dependent trap generation model in high-k metal gate MOS device with percolation simulation

High-k metal gate stacks are being used to suppress the gate leakage due to tunneling for sub-45 nm technology nodes.The reliability of thin dielectric films becomes a limitation to device manufacturing,especially to the breakdown characteristic.In this work,a breakdown simulator based on a percolation model and the kinetic Monte Carlo method is set up,and the intrinsic relation between time to breakdown and trap generation rate R is studied by TDDB simulation.It is found that all degradation factors,such as trap generation rate time exponent m,Weibull slope β and percolation factor s,each could be expressed as a function of trap density time exponent α.Based on the percolation relation and power law lifetime projection,a temperature related trap generation model is proposed.The validity of this model is confirmed by comparing with experiment results.For other device and material conditions,the percolation relation provides a new way to study the relationship between trap generation and lifetime projection.

Influence of multi-deposition multi-annealing on time-dependent dielectric breakdown characteristics of PMOS with high-k/metal gate last process

A multi-deposition multi-annealing technique （MDMA） is introduced into the process of high-k/metal gate MOSFET for the gate last process to effectively reduce the gate leakage and improve the device＇s performance. In this paper, we systematically investigate the electrical parameters and the time-dependent dielectric breakdown （TDDB） characteristics of positive channel metal oxide semiconductor （PMOS） under different MDMA process conditions, including the depo- sition/annealing （D＆A） cycles, the D＆A time, and the total annealing time. The results show that the increases of the number of D＆A cycles （from 1 to 2） and D＆A time （from 15 s to 30 s） can contribute to the results that the gate leakage current decreases by about one order of magnitude and that the time to fail （TTF） at 63.2% increases by about several times. However, too many D＆A cycles （such as 4 cycles） make the equivalent oxide thickness （EOT） increase by about 1A and the TTF of PMOS worsen. Moreover, different D＆A times and numbers of D＆A cycles induce different breakdown mechanisms.

Distributed Differences Structures Underlie Gating between the Kin Channel KAT1 and the Kout Channel SKOR

The family of voltage-gated （Shaker-like） potassium channels in plants includes both inward-rectifying （Kin） channels that allow plant cells to accumulate K＋ and outward-rectifying （Kout） channels that mediate K＋ efflux. Despite their dose structural similarities, Kin and Kout channels differ in their gating sensitivity towards voltage and the extracellular K＋ concentration. We have carried out a systematic program of domain swapping between the Kout channel SKOR and the Kin channel KAT1 to examine the impacts on gating of the pore regions, the S4, S5, and the S6 helices. We found that, in particular, the N-terminal part of the S5 played a critical role in KAT1 and SKOR gating. Our findings were supported by molecular dynamics of KAT1 and SKOR homology models. In silico analysis revealed that during channel opening and closing, displacement of certain residues, especially in the S5 and S6 segments, is more pronounced in KAT1 than in SKOR. From our analysis of the S4-S6 region, we conclude that gating （and K＋-sensing in SKOR） depend on a number of structural elements that are dispersed over this -145-residue sequence and that these place additional constraints on configurational rearrangement of the channels during gating.

‘C-type’ closed state and gating mechanisms of K2P channels revealed by conformational changes of the TREK-1 channel

Two-pore domain potassium (K2P) channels gate primarily within the selectivity filter, termed ‘C-type’ gating. Due to the lack of structural insights into the nonconductive (closed) state, ‘C-type’ gating mechanisms remain elusive. Here, molecular dynamics (MD) simulations on TREK-1, a K2P channel, revealed that M4 helix movements induce filter closing in a novel ‘deeper-down’ structure that represents a ‘C-type’ closed state. The ‘down’ structure does not represent the closed state as previously proposed and instead acts as an intermediate state in gating. The study identified the allosteric ‘seesaw’ mechanism of M4 helix movements in modulating filter closing. Finally, guided by this recognition of K2P gating mechanisms, MD simulations revealed that gain-of-function mutations and small-molecule activators activate TREK-1 by perturbing state transitions from open to closed states. Together, we reveal a ‘C-type’ closed state and provide mechanical insights into gating procedures and allosteric regulations for K2P channels.

Electrical Properties of Ultra Thin Nitride/Oxynitride Stack Dielectrics pMOS Capacitor with Refractory Metal Gate

Electrical properties of high quality ultra thin nitride/oxynitride(N/O)stack dielectrics pMOS capacitor with refractory metal gate electrode are investigated,and ultra thin (<2 nm) N/O stack gate dielectrics with significant low leakage current and high resistance to boron penetration are fabricated.Experiment results show that the stack gate dielectric of nitride/oxynitride combined with improved sputtered tungsten/titanium nitride (W/TiN) gate electrode is one of the candidates for deep sub-micron metal gate CMOS devices.

Modeling of Gate Tunneling Current for Nanoscale MOSFETs with High-k Gate Stacks

A quantum model based on solutions to the Schrodinger-Poisson equations is developed to investigate the device behavior related togate tunneling current for nanoscale MOSFETs with high-k gate stacks. This model can model various MOS device structures with combinations of high-k dielectric materials and multilayer gate stacks,revealing quantum effects on the device performance. Comparisons are made for gate current behavior between nMOSFET and pMOSFET high- k gate stack structures. The results presented are consistent with experimental data, whereas a new finding for an optimum nitrogen content in HfSiON gate dielectric requires further experimental verifications.

Double-gating mechanism and diversity of an adenosine triphosphate (ATP)-sensitive K^+ channel in neurons acutely dissociated from rat neocortex

Classically, ion channels are classified into 2 groups: chemical-sensitive (ligand-gated) and voltage-sensitive channels. Single ATP-sensitive K+ (K-ATP) channel currents were recorded in acutely dissociated rat neo-cortical neurons using patch clamp technique. A type of K-ATP channel has been found to be gated not only by intra-cellular ATP, but also by membrane potential ( Vm) , and proved to be a novel mechanism underlying the gating of ion channels, namely bi-gating mechanism. The results also show that the K-ATP channels possess heterogeneity and di-versity. These types of K-ATP channels have been identified in 40.12% of all patches, which are different in activa-tion-threshold and voltage-sensitivity. The present experiment studied the type-3 K-ATP channel with a unitary con-ductance of about 80 pS in detail ( n = 15). Taking account of all the available data, a variety of K-ATP channels are suggested to exist in body, and one type of them is bi-gated by both chemical substances and membrane potentials. This property of the K-ATP channels may be related to their pathophysiblogical function.

Gate Current for MOSFETs with High k Dielectric Materials

The MOSFET gate currents of high k gate dielectrics due to direct tunneling are investigated by using a new direct tunneling current model developed.The model includes both the inversion layer quantization effect with finite barrier height and the polysilicon depletion effect.The impacts of dielectric constant and conduction band offset as well as the band gap on the gate current are discussed.The results indicate that the gate dielectric materials with higher dielectric constant,larger conduction band offset and the larger band gap are necessary to reduce the gate current.The calculated results can be used as a guide to select the appropriate high k gate dielectric materials for MOSFETs.

MOS器件Hf基高k栅介质的研究综述

随着金属氧化物半导体(MOS)器件尺寸的持续缩小,HfO2因其介电常数(k)高、带隙大等特点,成为取代传统SiO2栅介质最有希望的候选材料.本文综述了Hf基高k栅介质薄膜的近年的研究进展.针对HfO2结晶温度低、在HfO2薄膜和Si衬底间易形成界面层导致漏电流大、界面态密度高、击穿电压低等问题,回顾了最近论文报道的两种策略,即掺杂改性和插入缓冲层.接着举例讨论了Hf基材料从二元到掺杂氧化物/复合物的演变、非Si衬底上淀积Hf基高k栅介质、Hf基高k栅介质的非传统MOS器件结构,为集成电路(IC)中MOS器件的长期发展提供一些思路.

Characterization of Sub-100nm MOSFETs with High K Gate Dielectric

The short-channel performance of typical 70nm MOSFETs with high K gate dielectric is widely studied by using a two dimensional(2-D) device simulator.The short-channel performance is degraded from the fringing field and lower the source/drain junction resistance.The sidewall material is found very useful to eliminate the fringing-induced berrier lowing effect.

Challenges in Atomic-Scale Characterization of High-k Dielectrics and Metal Gate Electrodes for Advanced CMOS Gate Stacks

The decreasing feature sizes in complementary metal-oxide semiconductor （CMOS） transistor technology will require the replacement of SiO2 with gate dielectrics that have a high dielectric constant （high-k） because as the SiO2 gate thickness is reduced below 1.4 nm, electron tunnelling effects and high leakage currents occur in SiO2, which present serious obstacles to future device reliability. In recent years significant progress has been made on the screening and selection of high-k gate dielectrics, understanding their physical properties, and their integration into CMOS technology. Now the family of hafnium oxide-based materials has emerged as the leading candidate for high-k gate dielectrics due to their excellent physical properties. It is also realized that the high-k oxides must be implemented in conjunction with metal gate electrodes to get sufficient potential for CMOS continue scaling. In the advanced nanoscale Si-based CMOS devices, the composition and thickness of interfacial layers in the gate stacks determine the critical performance of devices. Therefore, detailed atomic- scale understandings of the microstructures and interfacial structures built in the advanced CMOS gate stacks, are highly required. In this paper, several high-resolution electron, ion, and photon-based techniques currently used to characterize the high-k gate dielectrics and interfaces at atomic-scale, are reviewed. Particularly, we critically review the research progress on the characterization of interface behavior and structural evolution in the high-k gate dielectrics by high-resolution transmission electron microscopy （HRTEM） and the related techniques based on scanning transmission electron microscopy （STEM）, including high-angle annular dark- field （HAADF） imaging （also known as Z-contrast imaging）, electron energy-loss spectroscopy （EELS）, and energy dispersive X-ray spectroscopy （EDS）, due to that HRTEM and STEM have become essential metrology tools for characterizing the dielectric gate stacks in the present and future generations of CMOS devices. In Section 1 of this review, the working principles of each technique are briefly introduced and their key features are outlined. In Section 2, microstructural characterizations of high-k gate dielectrics at atomic-scale by electron microscopy are critically reviewed by citing some recent results reported on high-k gate dielectrics. In Section 3, metal gate electrodes and the interfacial structures between high-k dielectrics and metal gates are discussed. The electron beam damage effects in high-k gate stacks are also evaluated, and their origins and prevention are described in Section 4. Finally, we end this review with personal perspectives towards the future challenges of atomic-scale material characterization in advanced CMOS gate stacks.

High performance trench MOS barrier Schottky diode with high-k gate oxide

A novel trench MOS barrier Schottky diode（TMBS） device with a high-k material introduced into the gate insulator is reported, which is named high-k TMBS. By simulation with Medici, it is found that the high-k TMBS can have 19.8% lower leakage current while maintaining the same breakdown voltage and forward turn-on voltage compared with the conventional regular trench TMBS.

Current Progress of Hf(Zr)-Based High-k Gate Dielectric Thin Films

With the continued downscaling of complementary metal-oxide-semiconductor field effect transistor dimensions, high-dielectric constant （high-k） gate materials, as alternatives to SiO2, have been extensively investigated. Hf （Zr）-based high-k gate dielectric thin films have been regarded as the most promising candidates for high-k gate dielectric according to the International Technology Roadmap for Semiconductor due to their excellent physical properties and performance. This paper reviews the recent progress on Hf （Zr）-based high-k gate dielectrics based on PVD （physical vapor deposition） process. This article begins with a survey of various methods developed for generating Hf （Zr）-based high-k gate dielectrics, and then mainly focuses on microstructure, synthesis, characterization, formation mechanisms of interfacial layer, and optical properties of Hf （Zr）-based high-k gate dielectrics. Finally, this review concludes with personal perspectives towards future research on Hf （Zr）-based high-k gate dielectrics.

4H-SiC基功率器件的high-k栅介质材料研究进展

金属氧化物半导体场效应晶体管(MOSFET)作为碳化硅绝缘栅结构的典型器件被广泛使用,然而SiO_(2)介电常数低的缺点和SiO_(2)/4H-SiC界面特性差的问题一直制约着4H-SiC绝缘栅结构(金属-绝缘体-半导体,MIS)器件更大规模商业化应用,因此科研工作者一直致力于寻找能够替代或弥补SiO_(2)的high-k栅介质材料。本文对该科学问题的研究现状进行综述,首先指出合适的high-k栅介质材料应该拥有较宽的禁带宽度、较高的介电常数、良好的界面特性和热稳定性。然后,主要从栅薄膜制备工艺、沉积温度、栅介质界面特性和电学性能等方面对典型high-k栅介质材料的研究结果进行评价,包括氧化铪(HfO_(2))、氧化铝(Al_(2)O_(3))、氮化铝(AlN)、氧化钇(Y_(2)O_(3))、氧化铈(CeO_(2))、氧化锆(ZrO_(2))、氧化镧(La_(2)O_(3))、五氧化二钽(Ta_(2)O_(5))、钛酸钡(BaTiO_(3))、氧化钬(Ho_(2)O_(3))和由它们组合而成的堆栈栅介质。最后,对未来该领域的研究方向进行了展望和建议,例如对栅漏电流机理的研究、对新材料的更多尝试、器件在极端环境下的可靠性问题等。

The influence and explanation of fringing-induced barrier lowering on sub-100 nm MOSFETs with high-k gate dielectrics

The fringing-induced barrier lowering（FIBL） effect of sub-100 nm MOSFETs with high-k gate dielectrics is investigated using a two-dimensional device simulator.An equivalent capacitance theory is proposed to explain the physics mechanism of the FIBL effect.The FIBL effect is enhanced and the short channel performance is degraded with increasing capacitance.Based on equivalent capacitance theory,the influences of channel length,junction depth,gate/lightly doped drain（LDD） overlap length,spacer material and spacer width on FIBL is thoroughly investigated.A stack gate dielectric is presented to suppress the FIBL effect.

Key technologies for dual high-k and dual metal gate integration

The key technologies for the dual high-k and dual metal gate, such as the electrical optimization of metal insert poly-Si stack structure, the separating of high-k and metal gate of n/pMOS in different regions of the wafer, and the synchronous etching of n/pMOS gate stack, are successfully developed. First, reasonable flat-band voltage and equivalent oxide thickness of pMOS MIPS structure are obtained by further optimizing the HfSiAlON dielectric through incorporating more Al-O dipole at interface between HfSiAlON and bottom SiOx. Then, the separating of high-k and metal gate for n/pMOS is achieved by SC1（NH4OH：H2O2：H2O = 1 ： 1 ： 5） and DHF-based solution for the selective removing of n MOS TaN and Hf Si ON and by BCl3-based plasma and DHF-based solution for the selective removing of pMOS TaN/Mo and HfSiAlON.After that, the synchronous etching of n/pMOS gate stack is developed by utilizing optimized BCl3/SF6/O2/Ar plasma to obtain a vertical profile for TaN and TaN/Mo and by utilizing BCl3/Ar plasma combined with DHF-based solution to achieve high selectivity to Si substrate. Finally, good electrical characteristics of CMOS devices, obtained by utilizing these new developed technologies, further confirm that they are practicable technologies for DHDMG integration.

Analysis of flatband voltage shift of metal/high-k/SiO_2/Si stack based on energy band alignment of entire gate stack

A theoretical model of flatband voltage （VFB） of metal/high-k/Si02/Si stack is proposed based on band alignment of entire gate stack, i.e., the VFB is obtained by simultaneously considering band alignments of metal/high-k, high-k/SiO2 and SiO2/Si interfaces, and their interactions. Then the VFB of TiN/HfO2/SiO2/Si stack is experimentally obtained and theoretically investigated by this model. The theoretical calculations are in good agreement with the experimental results. Furthermore, both positive VFB shift of TiN/HfO2/SiO2/Si stack and Fermi level pinning are successfully interpreted and attributed to the dielectric contact induced gap states at TiN/HfO2 and HfO2/SiO2 interfaces.

Flat-band voltage shift in metal-gate/high-k/Si stacks

In metal-gate/high-k stacks adopted by the 45 nm technology node, the fiat-band voltage （Vfb） shift remains one of the most critical challenges, particularly the flat-band voltage roll-off （Vfb roll-off） phenomenon in p-channel metal- oxide-semiconductor （pMOS） devices with an ultrathin oxide layer. In this paper, recent progress on the investigation of the Vfb shift and the origin of the Vfb roll-off in the metal-gate/high-k pMOS stacks are reviewed. Methods that can alleviate the Vfb shift phenomenon are summarized and the future research trend is described.