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基于GPP-SDR的TD-HSDPA物理信道软件设计及优化
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作者 黄婕 黄敏 +2 位作者 张润福 齐心 赵利 《计算机工程与设计》 CSCD 北大核心 2012年第7期2584-2590,共7页
为了改善传统软件无线电开发方式的灵活性,降低开发成本,采用基于通用处理器的软件无线电(GPP-SDR)平台,研究了TD-HSDPA高速物理信道的实现及优化,包括HARQ功能模块的设计。通过优化接收机代码,极大提高了软件运行效率,对处理时延的测... 为了改善传统软件无线电开发方式的灵活性,降低开发成本,采用基于通用处理器的软件无线电(GPP-SDR)平台,研究了TD-HSDPA高速物理信道的实现及优化,包括HARQ功能模块的设计。通过优化接收机代码,极大提高了软件运行效率,对处理时延的测试结果表明,软件设计能够实现TD-HSDPA实时传输,并支持其高速物理信道协议栈在GPP-SDR平台上的高效运行。给出的HARQ仿真结果验证了系统的吞吐率性能。 展开更多
关键词 TD-SCDMA HSDPA gpp SDR HARQ
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GPP Based Open Cellular Network Towards 5G 被引量:2
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作者 Jiang Wang Jing Xu +1 位作者 Yang Yang Haidong Xu 《China Communications》 SCIE CSCD 2017年第6期189-198,共10页
Due to 5G's stringent and uncertainty traffic requirements,open ecosystem would be one inevitable way to develop 5G.On the other hand,GPP based mobile communication becomes appealing recently attributed to its str... Due to 5G's stringent and uncertainty traffic requirements,open ecosystem would be one inevitable way to develop 5G.On the other hand,GPP based mobile communication becomes appealing recently attributed to its striking advantage in flexibility and re-configurability.In this paper,both the advantages and challenges of GPP platform are detailed analyzed.Furthermore,both GPP based software and hardware architectures for open 5G are presented and the performances of real-time signal processing and power consumption are also evaluated.The evaluation results indicate that turbo and power consumption may be another challengeable problem should be further solved to meet the requirements of realistic deployments. 展开更多
关键词 3gpp 蜂窝网络 实时信号处理 生态系统 移动通信 硬件架构 涡轮增压 挑战性
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An FFT Performance Model for Optimizing General-Purpose Processor Architecture
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作者 李玲 陈云霁 +2 位作者 刘道福 钱诚 胡伟武 《Journal of Computer Science & Technology》 SCIE EI CSCD 2011年第5期875-889,共15页
General-purpose processor (GPP) is an important platform for fast Fourier transform (FFT),due to its flexibility,reliability and practicality.FFT is a representative application intensive in both computation and m... General-purpose processor (GPP) is an important platform for fast Fourier transform (FFT),due to its flexibility,reliability and practicality.FFT is a representative application intensive in both computation and memory access,optimizing the FFT performance of a GPP also benefits the performances of many other applications.To facilitate the analysis of FFT,this paper proposes a theoretical model of the FFT processing.The model gives out a tight lower bound of the runtime of FFT on a GPP,and guides the architecture optimization for GPP as well.Based on the model,two theorems on optimization of architecture parameters are deduced,which refer to the lower bounds of register number and memory bandwidth.Experimental results on different processor architectures (including Intel Core i7 and Godson-3B) validate the performance model.The above investigations were adopted in the development of Godson-3B,which is an industrial GPP.The optimization techniques deduced from our performance model improve the FFT performance by about 40%,while incurring only 0.8% additional area cost.Consequently,Godson-3B solves the 1024-point single-precision complex FFT in 0.368 μs with about 40 Watt power consumption,and has the highest performance-per-watt in complex FFT among processors as far as we know.This work could benefit optimization of other GPPs as well. 展开更多
关键词 fast Fourier transform (FFT) general-purpose processor (gpp performance prediction model vector unit DMA
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DSP技术的最新发展及其应用现状 被引量:22
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作者 魏晓云 陈杰 曾云 《半导体技术》 CAS CSCD 北大核心 2003年第9期18-21,共4页
概述了数字信号处理(DSP)技术的发展过程,分析比较了DSP处理器与通用微处理器(GPP)的异同;介绍了DSP的最新发展和应用现状;对数字信号处理技术的发展前景和趋势作了预测。
关键词 DSP技术 数字信号处理 通用微处理器 gpp 应用现状 发展前景
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面向应用的可重构编译器ASCRA(英文) 被引量:4
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作者 吴艳霞 顾国昌 +4 位作者 孙延腾 杨敏 杨杰 牛晓霞 孙霖 《计算机科学与探索》 CSCD 2011年第3期267-279,共13页
在很多应用领域已经开展了可重构计算的研究,但是由于缺乏高层设计工具,设计者需要较深的软件和硬件专业知识才能开发GPP/RAU架构的程序,阻碍了其大规模应用。提出了一种面向应用的可重构编译器——ASCRA的初始架构,它可以自动将C语言... 在很多应用领域已经开展了可重构计算的研究,但是由于缺乏高层设计工具,设计者需要较深的软件和硬件专业知识才能开发GPP/RAU架构的程序,阻碍了其大规模应用。提出了一种面向应用的可重构编译器——ASCRA的初始架构,它可以自动将C语言映射为VHDL语言,从而解决可重构计算中自动编译工具的瓶颈。ASCRA编译器主要研究软硬件划分技术和面向硬件的优化技术,如脉动阵列、循环流水技术。在ML505开发平台上,设计实现了ASCRA编译器的验证平台,并通过实验给出了核心程序段生成VHDL代码的综合信息。 展开更多
关键词 可重构编译 通用处理器(gpp)/可重构加速单元(RAU) 软硬划分 循环
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Reinventing Memory System Design for Many-Accelerator Architecture
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作者 王颖 张磊 +1 位作者 韩银和 李华伟 《Journal of Computer Science & Technology》 SCIE EI CSCD 2014年第2期273-280,共8页
The many-accelerator architecture, mostly composed of general-purpose cores and accelerator-like function units (FUs), becomes a great alternative to homogeneous chip multiprocessors (CMPs) for its superior power-... The many-accelerator architecture, mostly composed of general-purpose cores and accelerator-like function units (FUs), becomes a great alternative to homogeneous chip multiprocessors (CMPs) for its superior power-efficiency. However, the emerging many-accelerator processor shows a much more complicated memory accessing pattern than general purpose processors (GPPs) because the abundant on-chip FUs tend to generate highly-concurrent memory streams with distinct locality and bandwidth demand. The disordered memory streams issued by diverse accelerators exhibit a mutual- interference behavior and cannot be efficiently handled by the orthodox main memory interface that provides an inflexible data fetching mode. Unlike the traditional DRAM memory, our proposed Aggregation Memory System (AMS) can function adaptively to the characterized memory streams from different FUs, because it provides the FUs with different data fetching sizes and protects their locality in memory access by intelligently interleaving their data to memory devices through sub-rank binding. Moreover, AMS can batch the requests without sub-rank conflict into a read burst with our optimized memory scheduling policy. Experimental results from trace-based simulation show both conspicuous performance boost and energy saving brought by AMS. 展开更多
关键词 many-accelerator chip multiprocessor MEMORY general purpose processor
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