Particle swarm optimization algorithm is presented for the layout of ＂Integrate Circuit （IC）＂ design. Particle swarm optimization based on swarm intelligence is a new evolutionary computational tool and is success...Particle swarm optimization algorithm is presented for the layout of ＂Integrate Circuit （IC）＂ design. Particle swarm optimization based on swarm intelligence is a new evolutionary computational tool and is successfully applied in function optimization, neural network design, classification, pattern recognition, signal processing and robot technology and so on. A modified algorithm is presented and applied to the layout of IC design. For a given layout plane, first of all, this algorithm generates the corresponding grid group by barriers and nets＇ ports with the thought ofgridless net routing, establishes initialization fuzzy matrix, then utilizes the global optimization character to find out the best layout route only if it exits. The results of model simulation indicate that PSO algorithm is feasible and efficient in IC layout design.展开更多
A multi layer gridless area router is reported.Based on corner stitching,this router adopts tile expansion to explore path for each net.A heuristic method that penalizes nodes deviating from the destination is devise...A multi layer gridless area router is reported.Based on corner stitching,this router adopts tile expansion to explore path for each net.A heuristic method that penalizes nodes deviating from the destination is devised to accelerate the algorithm.Besides,an enhanced interval tree is used to manage the intermediate data structure.In order to improve the completion rate of routing,a new gridless rip up and rerouting algorithm is proposed.The experimental results indicate that the completion rate is improved after the rip up and reroute process and the speed of this algorithm is satisfactory.展开更多
A new gridless router to improve the yield of IC layout is presented. The improvement of yield is achieved by reducing the critical areas where the circuit failures are likely to happen. This gridless area router bene...A new gridless router to improve the yield of IC layout is presented. The improvement of yield is achieved by reducing the critical areas where the circuit failures are likely to happen. This gridless area router benefits from a novel cost function to compute critical areas during routing process, and heuristically lays the patterns on the chip area where it is less possible to induce critical area. The router also takes other objectives into consideration, such as routing completion rate and nets length. It takes advantage of gridless routing to gain more flexibility and a higher completion rate. The experimental results show that critical areas are effectively decreased by 21% on average while maintaining the routing completion rate over 99%.展开更多
文摘Particle swarm optimization algorithm is presented for the layout of ＂Integrate Circuit （IC）＂ design. Particle swarm optimization based on swarm intelligence is a new evolutionary computational tool and is successfully applied in function optimization, neural network design, classification, pattern recognition, signal processing and robot technology and so on. A modified algorithm is presented and applied to the layout of IC design. For a given layout plane, first of all, this algorithm generates the corresponding grid group by barriers and nets＇ ports with the thought ofgridless net routing, establishes initialization fuzzy matrix, then utilizes the global optimization character to find out the best layout route only if it exits. The results of model simulation indicate that PSO algorithm is feasible and efficient in IC layout design.
文摘A multi layer gridless area router is reported.Based on corner stitching,this router adopts tile expansion to explore path for each net.A heuristic method that penalizes nodes deviating from the destination is devised to accelerate the algorithm.Besides,an enhanced interval tree is used to manage the intermediate data structure.In order to improve the completion rate of routing,a new gridless rip up and rerouting algorithm is proposed.The experimental results indicate that the completion rate is improved after the rip up and reroute process and the speed of this algorithm is satisfactory.
基金Supported by the National Natural Science Foundation of China(NSFC)under Grant No.60476014.
文摘A new gridless router to improve the yield of IC layout is presented. The improvement of yield is achieved by reducing the critical areas where the circuit failures are likely to happen. This gridless area router benefits from a novel cost function to compute critical areas during routing process, and heuristically lays the patterns on the chip area where it is less possible to induce critical area. The router also takes other objectives into consideration, such as routing completion rate and nets length. It takes advantage of gridless routing to gain more flexibility and a higher completion rate. The experimental results show that critical areas are effectively decreased by 21% on average while maintaining the routing completion rate over 99%.
