Cascaded ELM-Based Joint Frame Synchronization and Channel Estimation over Rician Fading Channel with Hardware Imperfections

Due to the interdependency of frame synchronization(FS)and channel estimation(CE),joint FS and CE(JFSCE)schemes are proposed to enhance their functionalities and therefore boost the overall performance of wireless communication systems.Although traditional JFSCE schemes alleviate the influence between FS and CE,they show deficiencies in dealing with hardware imperfection(HI)and deterministic line-of-sight(LOS)path.To tackle this challenge,we proposed a cascaded ELM-based JFSCE to alleviate the influence of HI in the scenario of the Rician fading channel.Specifically,the conventional JFSCE method is first employed to extract the initial features,and thus forms the non-Neural Network(NN)solutions for FS and CE,respectively.Then,the ELMbased networks,named FS-NET and CE-NET,are cascaded to capture the NN solutions of FS and CE.Simulation and analysis results show that,compared with the conventional JFSCE methods,the proposed cascaded ELM-based JFSCE significantly reduces the error probability of FS and the normalized mean square error(NMSE)of CE,even against the impacts of parameter variations.

A Novel Quantization and Model Compression Approach for Hardware Accelerators in Edge Computing

Massive computational complexity and memory requirement of artificial intelligence models impede their deploy-ability on edge computing devices of the Internet of Things(IoT).While Power-of-Two(PoT)quantization is pro-posed to improve the efficiency for edge inference of Deep Neural Networks(DNNs),existing PoT schemes require a huge amount of bit-wise manipulation and have large memory overhead,and their efficiency is bounded by the bottleneck of computation latency and memory footprint.To tackle this challenge,we present an efficient inference approach on the basis of PoT quantization and model compression.An integer-only scalar PoT quantization(IOS-PoT)is designed jointly with a distribution loss regularizer,wherein the regularizer minimizes quantization errors and training disturbances.Additionally,two-stage model compression is developed to effectively reduce memory requirement,and alleviate bandwidth usage in communications of networked heterogenous learning systems.The product look-up table(P-LUT)inference scheme is leveraged to replace bit-shifting with only indexing and addition operations for achieving low-latency computation and implementing efficient edge accelerators.Finally,comprehensive experiments on Residual Networks(ResNets)and efficient architectures with Canadian Institute for Advanced Research(CIFAR),ImageNet,and Real-world Affective Faces Database(RAF-DB)datasets,indicate that our approach achieves 2×∼10×improvement in the reduction of both weight size and computation cost in comparison to state-of-the-art methods.A P-LUT accelerator prototype is implemented on the Xilinx KV260 Field Programmable Gate Array(FPGA)platform for accelerating convolution operations,with performance results showing that P-LUT reduces memory footprint by 1.45×,achieves more than 3×power efficiency and 2×resource efficiency,compared to the conventional bit-shifting scheme.

A High Efficiency Hardware Implementation of S-Boxes Based on Composite Field for Advanced Encryption Standard

The SubBytes (S-box) transformation is the most crucial operation in the AES algorithm, significantly impacting the implementation performance of AES chips. To design a high-performance S-box, a segmented optimization implementation of the S-box is proposed based on the composite field inverse operation in this paper. This proposed S-box implementation is modeled using Verilog language and synthesized using Design Complier software under the premise of ensuring the correctness of the simulation result. The synthesis results show that, compared to several current S-box implementation schemes, the proposed implementation of the S-box significantly reduces the area overhead and critical path delay, then gets higher hardware efficiency. This provides strong support for realizing efficient and compact S-box ASIC designs.

HARDWARE DEMODULATION METHOD FOR &D EDGEDETEOTION AND ERROR OOMPENSATION

A hardwale demodulation method for 2-D edge detection is proposed. The filtering step and the differential step are implemented by using the hardware circuit. This demodulation circuit simplifies the edgefinder and reduces the measuring cycle. The calibration method of scale setting is also presented,and bymeasuring some calibrated objects,the demodulation errors and the error correction table is obtained.

Spinal fusion-hardware construct: Basic concepts and imaging review

The interpretation of spinal images fixed with metallic hardware forms an increasing bulk of daily practice in a busy imaging department. Radiologists are required to be familiar with the instrumentation and operative options used in spinal fixation and fusion procedures, especially in his or her institute. This is critical in evaluating the position of implants and potential complications associated with the operative approaches and spinal fixation devices used. Thus, the radiologist can play an important role in patient care and outcome. This review outlines the advantages and disadvantages of commonly used imaging methods and reports on the best yield for each modality and how to overcome the problematic issues associated with the presence of metallic hardware during imaging. Baseline radiographs are essential as they are the baseline point for evaluation of future studies should patients develop symptoms suggesting possible complications. They may justify further imaging workup with computed tomography, magnetic resonance and/or nuclear medicine studies as the evaluation of a patient with a spinal implant involves a multi-modality approach. This review describes imaging features of potential complications associated with spinal fusion surgery as well as the instrumentation used. This basic knowledge aims to help radiologists approach everyday practice in clinical imaging.

Fault self-repair strategy based on evolvable hardware and reparation balance technology

In the face of harsh natural environment applications such as earth-orbiting and deep space satellites, underwater sea vehicles, strong electromagnetic interference and temperature stress,the circuits faults appear easily. Circuit faults will inevitably lead to serious losses of availability or impeded mission success without self-repair over the mission duration. Traditional fault-repair methods based on redundant fault-tolerant technique are straightforward to implement, yet their area, power and weight cost can be excessive. Moreover they utilize all plug-in or component level circuits to realize redundant backup, such that their applicability is limited. Hence, a novel selfrepair technology based on evolvable hardware（EHW） and reparation balance technology（RBT） is proposed. Its cost is low, and fault self-repair of various circuits and devices can be realized through dynamic configuration. Making full use of the fault signals, correcting circuit can be found through EHW technique to realize the balance and compensation of the fault output-signals. In this paper, the self-repair model was analyzed which based on EHW and RBT technique, the specific self-repair strategy was studied, the corresponding self-repair circuit fault system was designed, and the typical faults were simulated and analyzed which combined with the actual electronic devices. Simulation results demonstrated that the proposed fault self-repair strategy was feasible. Compared to traditional techniques, fault self-repair based on EHW consumes fewer hardware resources, and the scope of fault self-repair was expanded significantly.

Open-Source Hardware Is a Low-Cost Alternative for Scientific Instrumentation and Research

Scientific research requires the collection of data in order to study, monitor, analyze, describe, or understand a particular process or event. Data collection efforts are often a compromise: manual measurements can be time-consuming and labor-intensive, resulting in data being collected at a low frequency, while automating the data-collection process can reduce labor requirements and increase the frequency of measurements, but at the cost of added expense of electronic data-collecting instrumentation. Rapid advances in electronic technologies have resulted in a variety of new and inexpensive sensing, monitoring, and control capabilities which offer opportunities for implementation in agricultural and natural-resource research applications. An Open Source Hardware project called Arduino consists of a programmable microcontroller development platform, expansion capability through add-on boards, and a programming development environment for creating custom microcontroller software. All circuit-board and electronic component specifications, as well as the programming software, are open-source and freely available for anyone to use or modify. Inexpensive sensors and the Arduino development platform were used to develop several inexpensive, automated sensing and datalogging systems for use in agricultural and natural-resources related research projects. Systems were developed and implemented to monitor soil-moisture status of field crops for irrigation scheduling and crop-water use studies, to measure daily evaporation-pan water levels for quantifying evaporative demand, and to monitor environmental parameters under forested conditions. These studies demonstrate the usefulness of automated measurements, and offer guidance for other researchers in developing inexpensive sensing and monitoring systems to further their research.

System Outage Probability and Diversity Analysis of a SWIPT Based Two-Way DF Relay Network Under Transceiver Hardware Impairments

This paper investigates the system outage performance of a simultaneous wireless information and power transfer(SWIPT)based two-way decodeand-forward(DF)relay network,where potential hardware impairments(HIs)in all transceivers are considered.After harvesting energy and decoding messages simultaneously via a power splitting scheme,the energy-limited relay node forwards the decoded information to both terminals.Each terminal combines the signals from the direct and relaying links via selection combining.We derive the system outage probability under independent but non-identically distributed Nakagami-m fading channels.It reveals an overall system ceiling(OSC)effect,i.e.,the system falls in outage if the target rate exceeds an OSC threshold that is determined by the levels of HIs.Furthermore,we derive the diversity gain of the considered network.The result reveals that when the transmission rate is below the OSC threshold,the achieved diversity gain equals the sum of the shape parameter of the direct link and the smaller shape parameter of the terminalto-relay links;otherwise,the diversity gain is zero.This is different from the amplify-and-forward(AF)strategy,under which the relaying links have no contribution to the diversity gain.Simulation results validate the analytical results and reveal that compared with the AF strategy,the SWIPT based two-way relaying links under the DF strategy are more robust to HIs and achieve a lower system outage probability.

Hardware Performance Evaluation of SHA-3 Candidate Algorithms

Secure Hashing Algorithms (SHA) showed a significant importance in today’s information security applications. The National Institute of Standards and Technology (NIST), held a competition of three rounds to replace SHA1 and SHA2 with the new SHA-3, to ensure long term robustness of hash functions. In this paper, we present a comprehensive hardware evaluation for the final round SHA-3 candidates. The main goal of providing the hardware evaluation is to: find the best algorithm among them that will satisfy the new hashing algorithm standards defined by the NIST. This is based on a comparison made between each of the finalists in terms of security level, throughput, clock frequancey, area, power consumption, and the cost. We expect that the achived results of the comparisons will contribute in choosing the next hashing algorithm (SHA-3) that will support the security requirements of applications in todays ubiquitous and pervasive information infrastructure.

Fault Detection and Isolation for Low Hardware Redundancy Flight Control System

The problems of current highly redundant flight control system are analyzed in this paper. Our study gives methods of utilizing other information to reduce physical components on the condition of meeting the reliability requirements for flight control system. The strategies presented in this paper mainly include information redundancy, multi-thread, time redundancy, geometry space redundancy, etc.. Analysis and simulation show these non-hardware based methods can reduce the requirement of system hardware level and thus reduce the system complexity, weight, space, costs and R＆D （research and development） time.

Hardware/software partitioning based on dynamic combination of maximum entropy and chaos optimization algorithm

This paper presents an algorithm that combines the chaos optimization algorithm with the maximum entropy ( COA-ME) by using entropy model based on chaos algorithm,in which the maximum entropy is used as the second method of searching the excellent solution. The search direction is improved by chaos optimization algorithm and realizes the selective acceptance of wrong solution. The experimental result shows that the presented algorithm can be used in the partitioning of hardware/software of reconfigurable system. It effectively reduces the local extremum problem,and search speed as well as performance of partitioning is improved.

Exponential sine chaotification model for enhancing chaos and its hardware implementation

Chaotic systems have been intensively studied for their roles in many applications, such as cryptography, secure communications, nonlinear controls, etc. However, the limited complexity of existing chaotic systems weakens chaos-based practical applications. Designing chaotic maps with high complexity is attractive. This paper proposes the exponential sine chaotification model(ESCM), a method of using the exponential sine function as a nonlinear transform model, to enhance the complexity of chaotic maps. To verify the performance of the ESCM, we firstly demonstrated it through theoretical analysis. Then, to exhibit the high efficiency and usability of ESCM, we applied ESCM to one-dimensional(1D) and multidimensional(MD) chaotic systems. The effects were examined by the Lyapunov exponent and it was found that enhanced chaotic maps have much more complicated dynamic behaviors compared to their originals. To validate the simplicity of ESCM in hardware implementation, we simulated three enhanced chaotic maps using a digital signal processor(DSP). To explore the ESCM in practical application, we applied ESCM to image encryption. The results verified that the ESCM can make previous chaos maps competitive for usage in image encryption.

FAST ALGORITHM AND EFFICIENT HARDWARE ARCHITECTURE OF HALF-PIXEL INTERPOLATION UNIT FOR H.264/AVC

A fast half-pixel motion estimation algorithm and its corresponding hardware architecture are presented. Unlike three steps are needed in typical half-pixel motion estimation algorithm, the presented algorithm needs only two steps to obtain all the interpolated pixels of an entire 8′8 block. The proposed architecture works in a parallel way and is simulated by Modelsim 6.5 SE, synthesized to the Xilinx Virtex4 XC4VLX15 Field Programmable Gate Array(FPGA) device, and verified by hardware platform. The implementation results show that this architecture can achieve 190 MHz and 11 clock cycles are reduced to complete the entire interpolation process in comparison with typical half-pixel interpolation, which meets the requirements of real-time application for very high defination videos.

A Novel Pipelining Encryption Hardware System with High Throughput and High Integration for 5G

This paper presents a ZUC-256 stream cipher algorithm hardware system in order to prevent the advanced security threats for 5 G wireless network.The main innovation of the hardware system is that a six-stage pipeline scheme comprised of initialization and work stage is employed to enhance the solving speed of the critical logical paths.Moreover,the pipeline scheme adopts a novel optimized hardware structure to fast complete the Mod(231-1)calculation.The function of the hardware system has been validated experimentally in detail.The hardware system shows great superiorities.Compared with the same type system in recent literatures,the logic delay reduces by 47%with an additional hardware resources of only 4 multiplexers,the throughput rate reaches 5.26 Gbps and yields at least 45%better performance,the throughput rate per unit area increases 14.8%.The hardware system provides a faster and safer encryption module for the 5G wireless network.

Performance evaluation of a two-way relay network with energy harvesting^and hardware noises

In this paper,we propose a Two-Way Cognitive Relay Network(TWCRN)where the secondary users operate on an underlay mode to access the licensed bands.In the proposed protocols,two secondary sources transmit their data to a relay in the first time slot,and then the relay would forward the received information to both sources in the remaining time.Moreover,the relay is self-powered by harvesting energy from ambient Radio Frequency(RF)signals,using the Time Switching(TS)and the Power Switching(PS)method.This paper concentrates on eval-uating the performance of the secondary networks under the impact of hardware impairments and co-channel interference from the primary networks.In particular,based on the secondary transmitters'constraint power,we derive the closed-form expressions of the outage probability and the throughput over Rayleigh fading channels in two cases:TS and PS.We also investigate the energy efficiency issue and the locally optimal position of the relay to maximize the system throughput,which provides much information to install the relay location.Finally,our derivations are verified by Monte Carlo simulation.

Fuzzy and PI Controller Based SHAF for Mitigation of Current Harmonics with P-Q Method Using Matlab and RTDS Hardware

The main objective of this paper is to develop PI and Fuzzy logic controllers to analyse the performance of instantaneous real active and reactive power (p-q) control strategy for extracting reference currents of shunt active filters under balanced, un-balanced and balanced non-sinusoidal conditions. When the supply voltages are balanced and sinusoidal, then all controllers converge to the same compensation characteristics. However, when the supply voltages are distorted and/or un-balanced sinusoidal, these control strategies result in different degrees of compensation in harmonics. The p-q control strategy with PI controller is unable to yield an adequate solution when source voltages are not ideal. Extensive simulations were carried out;simulations were performed with balance, unbalanced and non sinusoidal conditions. Simulation results validate the dynamic behaviour of Fuzzy logic controller over PI controller. The 3-ph 4-wire SHAF system is also implemented on a Real Time Digital Simulator (RTDS Hardware) to further verify its effectiveness. The detailed simulation and RTDS Hardware results are included.

Quasi-cyclic Random Projection Code and Hardware Implementation

Random Projection Code (RPC) is a mechanism that combines channel coding and modulation together and realizes rate adaptation in the receiving end. Random projection code’s mapping matrix has significant influences on decoding performance as well as hardware implementation complexity. To reduce hardware implementation complexity, we design a quasi-cyclic mapping matrix for RPC codes. Compared with other construction approaches, our design gets rid of data filter component, thus reducing chip area 7284.95 um2, and power consumption 331.46 uW in 0.13 um fabrication. Our simulation results show that our method does not cause any performance loss and even gets 0.2 dB to 0.5 dB gain at BER 10-4.

Neural Networks on an FPGA and Hardware-Friendly Activation Functions

This paper describes our implementation of several neural networks built on a field programmable gate array (FPGA) and used to recognize a handwritten digit dataset—the Modified National Institute of Standards and Technology (MNIST) database. We also propose a novel hardware-friendly activation function called the dynamic Rectifid Linear Unit (ReLU)—D-ReLU function that achieves higher performance than traditional activation functions at no cost to accuracy. We built a 2-layer online training multilayer perceptron (MLP) neural network on an FPGA with varying data width. Reducing the data width from 8 to 4 bits only reduces prediction accuracy by 11%, but the FPGA area decreases by 41%. Compared to networks that use the sigmoid functions, our proposed D-ReLU function uses 24% - 41% less area with no loss to prediction accuracy. Further reducing the data width of the 3-layer networks from 8 to 4 bits, the prediction accuracies only decrease by 3% - 5%, with area being reduced by 9% - 28%. Moreover, FPGA solutions have 29 times faster execution time, even despite running at a 60× lower clock rate. Thus, FPGA implementations of neural networks offer a high-performance, low power alternative to traditional software methods, and our novel D-ReLU activation function offers additional improvements to performance and power saving.

Virtual-reality and intelligent hardware in Digital Twins

Several new models and formats for the digital transformation of the manufacturing industry appear because of the rapid integration of information technology and the real economy,as well as the increasingly obvious evolution trend of industrial digitalization,networking,and intelligence.Among them,digital twins have increasingly become a research hotspot in all sectors of the industry and have broad prospects.It maps physical objects in virtual space in a digital way and simulates their behavioral characteristics in real environments.It makes the gap between virtuality and reality disappear based on their closed-loop interaction.Digital twins are undoubtedly an important and strategic technology in response to familiar products,production,and services.It can also speculate some indicators that cannot be directly measured by machine learning through collecting the direct data of limited physical sensor indicators.This can realize an assessment of the current state,a diagnosis of past problems,and a prediction of future trends,and simulate possibilities to provide more comprehensive decision support.

Virtual-reality and intelligent hardware in digital twins

Several new models and formats for the digital transformation of the manufacturing industry appear because of the rapid integration of information technology and the real economy,as well as the increasingly obvious evolution trend of industrial digitalization,networking,and intelligence.Among them,digital twins have increasingly become a research hotspot in all sectors of the industry and have broad prospects.It maps physical objects in virtual space in a digital way and simulates their behavioral characteristics in real environments.It makes the gap between virtuality and reality disappear based on their closed-loop interaction.Digital twins are undoubtedly an important and strategic technology in response to familiar products,production,and services.It can also speculate some indicators that cannot be directly measured by machine learning through collecting the direct data of limited physical sensor indicators.This can realize an assessment of the current state,a diagnosis of past problems,and a prediction of future trends,and simulate possibilities to provide more comprehensive decision support.