Dynamics analysis and cryptographic implementation of a fractional-order memristive cellular neural network model

Due to the fact that a memristor with memory properties is an ideal electronic component for implementation of the artificial neural synaptic function,a brand-new tristable locally active memristor model is first proposed in this paper.Here,a novel four-dimensional fractional-order memristive cellular neural network(FO-MCNN)model with hidden attractors is constructed to enhance the engineering feasibility of the original CNN model and its performance.Then,its hardware circuit implementation and complicated dynamic properties are investigated on multi-simulation platforms.Subsequently,it is used toward secure communication application scenarios.Taking it as the pseudo-random number generator(PRNG),a new privacy image security scheme is designed based on the adaptive sampling rate compressive sensing(ASR-CS)model.Eventually,the simulation analysis and comparative experiments manifest that the proposed data encryption scheme possesses strong immunity against various security attack models and satisfactory compression performance.

A novel multi-scroll chaotic generator:Analysis, simulation, and implementation

Based on a new three-dimensional autonomous linear system and designing a specific form of saturated function series and a sign function with two variables of system, which are employed to increase saddle-focus equilibrium points with index 2, a novel multi-scroll chaotic system is proposed and its typical dynamical characteristics including bifurcation diagram, Poincare map, and the stability of equilibrium points are analyzed. The hardware circuit is designed and the experimental results are presented for confirmation.

SF^2HDL： A Computational Tool of State Transition Diagram Translation

The lack of standard to electronic circuits modeling made possible the development of many tools and modeling languages for electronic circuits. In this way, several tools to be used on different descriptions stage of the designs are necessary. This paper presents a tool called SF^2HDL （Stateflow to Hardware Description Language or State Transition Table） that translates a finite state machine on state transition diagram representation, described by Stateflow tool, into an input file standard for TABELA program or into a file behavioral VHDL （Very High Speed Integrated Circuits Hardware Description Language） directly. The TABELA program was used to optimization this finite state machine. After that, the TAB2VHDL program was used to generate the VHDL code on register transfer level, what permits comparisons with results obtained by synthesis. The finite state machine must be described by Mealy model and the user can describe the machine on high level abstraction using all Simulink supports. The tool was very efficient on computational cost and it made translation of several cases, for the two VHDL description models. Every state machine translated was simulated and implemented on device EP2C20F484C7 using Quartus II environment.

Design and implementation of high-speed real-time data acquisition system based on FPGA

The electromagnetic radiation will result in informa- tion leakage being recovered when computers work. This article presents a high-speed real-time data acquisition system based on peripheral component interconnect （PCI） bus and field programmable gate array （FPGA） for sampling electromagnetic radiation caused by video signal. The hardware design and controlling flow of each module are introduced in detail. The sampling rate can reach 64 Msps and system transfers speed can be up to 128 Mb/s by using time interleaving, which increases the overall sampling speed of a system by operating two data converters in parallel.

Development of a PVDF sensor for potted seedling clamping force of vegetable transplanting

Aiming at the problems of loose bowl,nutritive bowl damage and planting leakage caused by lack of perception and detection of seedling clamping force in vegetable transplanting,a semi-micro-column structure sensor for measuring potted seedling clamping force was developed based on polyvinylidene fluoride(PVDF)piezoelectric film.The diameter of the semi-micro-column is 4 mm.The size of the force probe is 14 mm×30 mm,the encapsulation position of the force probe is 25 mm away from the tip of the seedling claw.The hardware circuit for sensor signal acquisition including pre-amplification module,power frequency notch module,low-pass filter module,processor module and power module was designed.The circuit completes charge-voltage conversion,clamping force signal amplification,power frequency signal elimination,vibration and noise elimination,and ensures the accurate acquisition of clamping force signal.In order to verify the sensor performance,sensor calibration tests and indoor experiments were carried out respectively.The calibration tests showed that the sensitivity of the clamping force sensor was 0.5264 V/N,the linearity was 4.74%,the accuracy was 6.51%,the hysteresis was 3.63%,and the range was 8 N under the impact of different waveforms and frequencies,which fully meet the accuracy requirements of the clamping force detection during transplanting.Indoor experiments showed that the clamping force sensor had good stability and adaptability under different seedling frequencies.The sensor can provide useful reference for the perception and detection of seedling clamping force and the feedback regulation of seedling clamping force.

Realization of Communication Protocols of RFID R/W Device Based on CPLD

The function of the communication module of Radio FrequencyIdentification(RFID)system is de- scribed. Based on Electronic DesignAutomation(EDA), the implementation of digital module of RFID usingXIL- INX XC9500 series Complex Programmable Logic Device(CPLD)isintroduced modularized and layering methods In communicationprotocols of RFID systems are employed to enhance the systemperformance and facilitate the de- Sign. To ensure the security andreliability of data transmission, a new method of combing encryptionand error cor- Rection is employed and described in detail.