Cascaded ELM-Based Joint Frame Synchronization and Channel Estimation over Rician Fading Channel with Hardware Imperfections

Due to the interdependency of frame synchronization(FS)and channel estimation(CE),joint FS and CE(JFSCE)schemes are proposed to enhance their functionalities and therefore boost the overall performance of wireless communication systems.Although traditional JFSCE schemes alleviate the influence between FS and CE,they show deficiencies in dealing with hardware imperfection(HI)and deterministic line-of-sight(LOS)path.To tackle this challenge,we proposed a cascaded ELM-based JFSCE to alleviate the influence of HI in the scenario of the Rician fading channel.Specifically,the conventional JFSCE method is first employed to extract the initial features,and thus forms the non-Neural Network(NN)solutions for FS and CE,respectively.Then,the ELMbased networks,named FS-NET and CE-NET,are cascaded to capture the NN solutions of FS and CE.Simulation and analysis results show that,compared with the conventional JFSCE methods,the proposed cascaded ELM-based JFSCE significantly reduces the error probability of FS and the normalized mean square error(NMSE)of CE,even against the impacts of parameter variations.

A Novel Quantization and Model Compression Approach for Hardware Accelerators in Edge Computing

Massive computational complexity and memory requirement of artificial intelligence models impede their deploy-ability on edge computing devices of the Internet of Things(IoT).While Power-of-Two(PoT)quantization is pro-posed to improve the efficiency for edge inference of Deep Neural Networks(DNNs),existing PoT schemes require a huge amount of bit-wise manipulation and have large memory overhead,and their efficiency is bounded by the bottleneck of computation latency and memory footprint.To tackle this challenge,we present an efficient inference approach on the basis of PoT quantization and model compression.An integer-only scalar PoT quantization(IOS-PoT)is designed jointly with a distribution loss regularizer,wherein the regularizer minimizes quantization errors and training disturbances.Additionally,two-stage model compression is developed to effectively reduce memory requirement,and alleviate bandwidth usage in communications of networked heterogenous learning systems.The product look-up table(P-LUT)inference scheme is leveraged to replace bit-shifting with only indexing and addition operations for achieving low-latency computation and implementing efficient edge accelerators.Finally,comprehensive experiments on Residual Networks(ResNets)and efficient architectures with Canadian Institute for Advanced Research(CIFAR),ImageNet,and Real-world Affective Faces Database(RAF-DB)datasets,indicate that our approach achieves 2×∼10×improvement in the reduction of both weight size and computation cost in comparison to state-of-the-art methods.A P-LUT accelerator prototype is implemented on the Xilinx KV260 Field Programmable Gate Array(FPGA)platform for accelerating convolution operations,with performance results showing that P-LUT reduces memory footprint by 1.45×,achieves more than 3×power efficiency and 2×resource efficiency,compared to the conventional bit-shifting scheme.

A High Efficiency Hardware Implementation of S-Boxes Based on Composite Field for Advanced Encryption Standard

The SubBytes (S-box) transformation is the most crucial operation in the AES algorithm, significantly impacting the implementation performance of AES chips. To design a high-performance S-box, a segmented optimization implementation of the S-box is proposed based on the composite field inverse operation in this paper. This proposed S-box implementation is modeled using Verilog language and synthesized using Design Complier software under the premise of ensuring the correctness of the simulation result. The synthesis results show that, compared to several current S-box implementation schemes, the proposed implementation of the S-box significantly reduces the area overhead and critical path delay, then gets higher hardware efficiency. This provides strong support for realizing efficient and compact S-box ASIC designs.

Wavelet Denoising Applied to Hardware Redundant Systems for Rolling Element Bearing Fault Detection

This work presents a novel wavelet-based denoising technique for improving the signal-to-noise ratio(SNR)of nonsteady vibration signals in hardware redundant systems.The proposed method utilizes the relationship between redundant hardware components to effectively separate fault-related components from the vibration signature,thus enhancing fault detection accuracy.The study evaluates the proposed technique on two mechanically identical subsystems that are simultaneously controlled under the same speed and load inputs,with and without the proposed denoising step.The results demonstrate an increase in detection accuracy when incorporating the proposed denoising method into a fault detection system designed for hardware redundant machinery.This work is original in its application of a new method for improving performance when using residual analysis for fault detection in hardware redundant machinery configurations.Moreover,the proposed methodology is applicable to nonstationary equipment that experiences changes in both speed and load.

Treatment and Hardware Removal after Lisfranc Injury: A Narrative Review

Lisfranc injuries can be difficult injuries to identify and treat, while also being the subject of significant debate on proper surgical management. A narrative literature review was performed using Pubmed and Google Scholar databases to identify recent studies evaluating open reduction internal fixation vs primary arthrodesis for Lisfranc injuries to further elucidate optimal surgical management. Additional focus was placed removal of hardware after ORIF to identify the need for routine hardware removal as an additional surgery may guide surgeon decision-making. This review showed inconclusive data on the superiority of ORIF vs arthrodesis, as multiple conflicting results exist, though established that functional results are similar between these options. Though both are generally accepted treatment options, there are no well-designed randomized controlled trials directly comparing the two. Retention of hardware after ORIF has been shown to be tolerated, though there is a significant risk of the need for unplanned removal due to pain and hardware breakage.

FPGA based hardware platform for trapped-ion-based multi-level quantum systems

We report a design and implementation of a field-programmable-gate-arrays(FPGA)based hardware platform,which is used to realize control and signal readout of trapped-ion-based multi-level quantum systems.This platform integrates a four-channel 2.8 Gsps@14 bits arbitrary waveform generator,a 16-channel 1 Gsps@14 bits direct-digital-synthesisbased radio-frequency generator,a 16-channel 8 ns resolution pulse generator,a 10-channel 16 bits digital-to-analogconverter module,and a 2-channel proportion integration differentiation controller.The hardware platform can be applied in the trapped-ion-based multi-level quantum systems,enabling quantum control of multi-level quantum system and highdimensional quantum simulation.The platform is scalable and more channels for control and signal readout can be implemented by utilizing more parallel duplications of the hardware.The hardware platform also has a bright future to be applied in scaled trapped-ion-based quantum systems.

List-Serial Pipelined Hardware Architecture for SCL Decoding of Polar Codes

For polar codes,the performance of successive cancellation list(SCL)decoding is capable of approaching that of maximum likelihood decoding.However,the existing hardware architectures for the SCL decoding suffer from high hardware complexity due to calculating L decoding paths simultaneously,which are unfriendly to the devices with limited logical resources,such as field programmable gate arrays(FPGAs).In this paper,we propose a list-serial pipelined hardware architecture with low complexity for the SCL decoding,where the serial calculation and the pipelined operation are elegantly combined to strike a balance between the complexity and the latency.Moreover,we employ only one successive cancellation(SC)decoder core without L×L crossbars,and reduce the number of inputs of the metric sorter from 2L to L+2.Finally,the FPGA implementations show that the hardware resource consumption is significantly reduced with negligible decoding performance loss.

Exploiting the Direct Link in IRS Assisted NOMA Networks with Hardware Impairments

Hardware impairments(HI)are always present in low-cost wireless devices.This paper investigates the outage behaviors of intelligent reflecting surface(IRS)assisted non-orthogonal multiple access(NOMA)networks by taking into account the impact of HI.Specifically,we derive the approximate and asymptotic expressions of the outage probability for the IRS-NOMA-HI networks.Based on the asymptotic results,the diversity orders under perfect self-interference cancellation and imperfect self-interference cancellation scenarios are obtained to evaluate the performance of the considered network.In addition,the system throughput of IRS-NOMA-HI is discussed in delay-limited mode.The obtained results are provided to verify the accuracy of the theoretical analyses and reveal that:1)The outage performance and system throughput for IRS-NOMA-HI outperforms that of the IRS-assisted orthogonal multiple access-HI(IRS-OMA-HI)networks;2)The number of IRS elements,the pass loss factors,the Rician factors,and the value of HI are pivotal to enhancing the performance of IRS-NOMAHI networks;and 3)It is recommended that effective methods of reducing HI should be used to ensure system performance,in addition to self-interference cancellation techniques.

System Outage Probability and Diversity Analysis of a SWIPT Based Two-Way DF Relay Network Under Transceiver Hardware Impairments

This paper investigates the system outage performance of a simultaneous wireless information and power transfer(SWIPT)based two-way decodeand-forward(DF)relay network,where potential hardware impairments(HIs)in all transceivers are considered.After harvesting energy and decoding messages simultaneously via a power splitting scheme,the energy-limited relay node forwards the decoded information to both terminals.Each terminal combines the signals from the direct and relaying links via selection combining.We derive the system outage probability under independent but non-identically distributed Nakagami-m fading channels.It reveals an overall system ceiling(OSC)effect,i.e.,the system falls in outage if the target rate exceeds an OSC threshold that is determined by the levels of HIs.Furthermore,we derive the diversity gain of the considered network.The result reveals that when the transmission rate is below the OSC threshold,the achieved diversity gain equals the sum of the shape parameter of the direct link and the smaller shape parameter of the terminalto-relay links;otherwise,the diversity gain is zero.This is different from the amplify-and-forward(AF)strategy,under which the relaying links have no contribution to the diversity gain.Simulation results validate the analytical results and reveal that compared with the AF strategy,the SWIPT based two-way relaying links under the DF strategy are more robust to HIs and achieve a lower system outage probability.

Temperature-Triggered Hardware Trojan Based Algebraic Fault Analysis of SKINNY-64-64 Lightweight Block Cipher

SKINNY-64-64 is a lightweight block cipher with a 64-bit block length and key length,and it is mainly used on the Internet of Things(IoT).Currently,faults can be injected into cryptographic devices by attackers in a variety of ways,but it is still difficult to achieve a precisely located fault attacks at a low cost,whereas a Hardware Trojan(HT)can realize this.Temperature,as a physical quantity incidental to the operation of a cryptographic device,is easily overlooked.In this paper,a temperature-triggered HT(THT)is designed,which,when activated,causes a specific bit of the intermediate state of the SKINNY-64-64 to be flipped.Further,in this paper,a THT-based algebraic fault analysis(THT-AFA)method is proposed.To demonstrate the effectiveness of the method,experiments on algebraic fault analysis(AFA)and THT-AFA have been carried out on SKINNY-64-64.In the THT-AFA for SKINNY-64-64,it is only required to activate the THT 3 times to obtain the master key with a 100%success rate,and the average time for the attack is 64.57 s.However,when performing AFA on this cipher,we provide a relation-ship between the number of different faults and the residual entropy of the key.In comparison,our proposed THT-AFA method has better performance in terms of attack efficiency.To the best of our knowledge,this is the first HT attack on SKINNY-64-64.

Hardware Security for IoT in the Quantum Era: Survey and Challenges

The Internet of Things (IoT) has become a reality: Healthcare, smart cities, intelligent manufacturing, e-agriculture, real-time traffic controls, environment monitoring, camera security systems, etc. are developing services that rely on an IoT infrastructure. Thus, ensuring the security of devices during operation and information exchange becomes a fundamental requirement inherent in providing safe and reliable IoT services. NIST requires hardware implementations that are protected against SCAs for the lightweight cryptography standardization process. These attacks are powerful and non-invasive and rely on observing the physical properties of IoT hardware devices to obtain secret information. In this paper, we present a survey of research on hardware security for the IoT. In addition, the challenges of IoT in the quantum era with the first results of the NIST standardization process for post-quantum cryptography are discussed.

Secrecy Outage Probability for Two-Way Integrated Satellite Unmanned Aerial Vehicle Relay Networks with Hardware Impairments

In this paper,we investigate the secrecy outage performance for the two-way integrated satellite unmanned aerial vehicle relay networks with hardware impairments.Particularly,the closed-form expression for the secrecy outage probability is obtained.Moreover,to get more information on the secrecy outage probability in a high signalto-noise regime,the asymptotic analysis along with the secrecy diversity order and secrecy coding gain for the secrecy outage probability are also further obtained,which presents a fast method to evaluate the impact of system parameters and hardware impairments on the considered network.Finally,Monte Carlo simulation results are provided to show the efficiency of the theoretical analysis.

工科专业虚实结合实践教学方式应用研究

随着工科高等教育改革的推进和行业发展需求的变化,实践教学改革势在必行。针对工科专业实践教学现状,结合硬件在环和数字孪生两种实践教学手段,阐述虚实结合实践教学方式的优势。在此基础上对运动控制系统和可编程控制器两门课程的虚实结合实践教学应用进行分析讨论。实践表明,虚实结合实践教学方式对学生完成理论知识内化、提升实践能力和创新能力具有显著的促进作用。

面向边缘计算的可重构CNN协处理器研究与设计

随着深度学习技术的发展,卷积神经网络模型的参数量和计算量急剧增加,极大提高了卷积神经网络算法在边缘侧设备的部署成本。因此,为了降低卷积神经网络算法在边缘侧设备上的部署难度,减小推理时延和能耗开销,该文提出一种面向边缘计算的可重构CNN协处理器结构。基于按通道处理的数据流模式,提出的两级分布式存储方案解决了片上大规模的数据搬移和重构运算时PE单元间的大量数据移动导致的功耗开销和性能下降的问题;为了避免加速阵列中复杂的数据互联网络传播机制,降低控制的复杂度,该文提出一种灵活的本地访存机制和基于地址转换的填充机制,使得协处理器能够灵活实现任意规格的常规卷积、深度可分离卷积、池化和全连接运算,提升了硬件架构的灵活性。本文提出的协处理器包含256个PE运算单元和176 kB的片上私有存储器,在55 nm TT Corner(25°C,1.2 V)的CMOS工艺下进行逻辑综合和布局布线,最高时钟频率能够达到328 MHz,实现面积为4.41 mm^(2)。在320 MHz的工作频率下,该协处理器峰值运算性能为163.8 GOPs,面积效率为37.14GOPs/mm^(2),完成LeNet-5和MobileNet网络的能效分别为210.7 GOPs/W和340.08 GOPs/W,能够满足边缘智能计算场景下的能效和性能需求。

制导控制系统半实物仿真总体方案设计及集成联试

半实物仿真作为一个大型分布式仿真系统,其总体方案的设计优劣和集成联试的是否顺利,直接影响了系统性能指标的表现和建设目标的实现。归纳总结了总体方案设计的工作内容,分析了实时性、兼容性、扩展性和安全性的性能要求;给出了包括功能层次、运行机制和结构组成在内的典型半实物仿真系统总体方案;概括了仿真系统的集成联试内容,总结了典型系统的集成联试步骤,给出了系统验收测试的内容和系统可信度评估方法。

基于卷积神经网络的岩渣分类算法及其FPGA加速

全断面岩石掘进机在道路掘进过程中,刀盘挤压切削岩体容易产生刀盘磨损及损坏,从而造成经济损失,因此需要检测刀盘磨损的理论和技术来指导施工。岩渣是掘进过程的直接产物,携带丰富的信息,能够反映当前的施工状况,因此可以通过岩渣识别利用这些信息间接实现对刀盘的监测。提出了一种基于卷积神经网络的岩渣识别算法,在岩渣数据集上实现了96.5%的分类准确率。随后为了便于FPGA硬件部署,提出一种网络压缩方法,将网络规模压缩到原始网络的2.28%,同时分类准确率相比原网络仅下降了0.9%。最后使用OpenCL技术在Intel Arria 10 GX1150平台上实现了算法部署,达到了224.54 GOP/s的吞吐率以及11.23 GOP/s/W的能效比。

基于人工蜂群算法的温差发电阵列最优重构方法

在新能源发电技术快速发展的背景下,温差发电(TEG)技术能够很好地利用新能源发电中产生的废热.然而,温度分布的变化会使得TEG阵列的输出特性恶化、发电效率降低.提出基于人工蜂群(ABC)算法的TEG阵列重构方法,在3种不同温度分布情况下,利用ABC在对称9×9和不对称10×15两种TEG阵列进行动态重构.将所提算法与遗传算法、粒子群优化算法和秃鹰搜索优化算法3种启发式算法作对比,并给出由ABC重构后的TEG阵列温度分布图.结果表明:ABC能够提高TEG阵列的输出功率,输出功率-电压曲线均趋向呈现出单个峰值.此外,利用基于RTLAB平台上的硬件在环实验验证了硬件可行性.

玉米联合收获机清选控制系统设计与试验

玉米联合收获机清选系统工况复杂,存在收获质量差、效率不高等问题。基于此,设计一套清选损失率控制为主同时兼顾含杂率的自动控制系统。首先分析以风机转速、振动筛转速和喂入量为影响因素,损失率、含杂率为评价指标的正交试验数据,获取影响损失率和含杂率的主次因素,提出清选系统自动控制策略;其次,为开展控制策略和算法的研究,建立清选系统中的风机转速、振动筛转速调节装置以及收获机纵向运动的数学模型,设计离散化PID控制算法。最后,基于MATLAB/dSPACE软硬件环境,搭建清选控制系统的硬件在环仿真平台,并进行控制器在环测试。试验证明:本文设定的双目标联合控制策略和控制算法,能够有效降低清选损失率、含杂率,其中清选损失率降到2.7%左右,含杂率为2.8%左右。

通用信道编译码算法物理性能快速仿真系统

为实现信道编译码硬件算法物理性能的快速、准确验证,提出一种软硬件协同的通用化信道编译码算法物理性能快速仿真与性能评估系统。PC上位机软件主要实现模拟信源/噪声数据生成、仿真数据后分析、数据/控制指令传输以及与FPGA下位机交互等功能;FPGA下位机通过设计数据调度与系统控制、信道编译码算法架构、加噪信道以及数据统计等单元,构建通用编译码算法验证系统硬件系统架构,支持不同信道编译码算法物理性能的高效、准确验证。以系统当前支持的BCH码、LDPC码、删余卷积码、RS码及其串行级联码的性能仿真为例开展性能测试,性能恶化最大值低于0.4 dB,在10-7误码率统计量级下,仿真时间低于12 s,验证仿真评估系统的准确性、可靠性与有效性。系统采用的通用级联架构还可支持其他信道编译码算法的快速移植与部署,可为信道编译码算法物理性能快速验证提供一种有效的解决方案。

集成式电液制动系统自适应压力控制

针对集成式电液制动系统(integrated electro-hydraulic brake system,IEHB)存在的复杂液压非线性特性和时变摩擦干扰,提出一种自适应压力控制策略。外环压力控制器引入液压特性的动态线性化模型并基于滑模观测器对模型参数实时辨识实现对非线性液压特性的自适应。内环伺服控制器采用基于压力的连续摩擦补偿和反步动态面控制应对传动机构摩擦阻碍。硬件在环实验结果表明,与现有的先进级联压力控制相比,设计的压力控制策略在多种工况下均表现出更高的控制精度和鲁棒性,并显著提升了IEHB在不同液压回路结构下的压力控制效果。