Towards High-Performance Graph Processing: From a Hardware/Software Co-Design Perspective

Graph processing has been widely used in many scenarios,from scientific computing to artificial intelligence.Graph processing exhibits irregular computational parallelism and random memory accesses,unlike traditional workloads.Therefore,running graph processing workloads on conventional architectures(e.g.,CPUs and GPUs)often shows a significantly low compute-memory ratio with few performance benefits,which can be,in many cases,even slower than a specialized single-thread graph algorithm.While domain-specific hardware designs are essential for graph processing,it is still challenging to transform the hardware capability to performance boost without coupled software codesigns.This article presents a graph processing ecosystem from hardware to software.We start by introducing a series of hardware accelerators as the foundation of this ecosystem.Subsequently,the codesigned parallel graph systems and their distributed techniques are presented to support graph applications.Finally,we introduce our efforts on novel graph applications and hardware architectures.Extensive results show that various graph applications can be efficiently accelerated in this graph processing ecosystem.

An efficient GPU-based parallel tabu search algorithm for hardware/software co-design

Hardware/software partitioning is an essential step in hardware/software co-design.For large size problems,it is difficult to consider both solution quality and time.This paper presents an efficient GPU-based parallel tabu search algorithm(GPTS)for HW/SW partitioning.A single GPU kernel of compacting neighborhood is proposed to reduce the amount of GPU global memory accesses theoretically.A kernel fusion strategy is further proposed to reduce the amount of GPU global memory accesses of GPTS.To further minimize the transfer overhead of GPTS between CPU and GPU,an optimized transfer strategy for GPU-based tabu evaluation is proposed,which considers that all the candidates do not satisfy the given constraint.Experiments show that GPTS outperforms state-of-the-art work of tabu search and is competitive with other methods for HW/SW partitioning.The proposed parallelization is significant when considering the ordinary GPU platform.

Hardware/software co-verification platform for EOS design

Ethernet over SDH/SONET (EOS) is a hotspot in today's data transmission technology for it combines the merits of both Ethernet and SDH/SONET. However, implementing an EOS system on a chip is complex and needs full verifications. This paper introduces our design of Hardware/Software co-verification platform for EOS design. The hardware platform contains a microprocessor board and an FPGA (Field Programmable Gate Array)-based verification board, and the corresponding software includes test benches running in FPGAs, controlling programs for the microprocessor and a console program with GUI (Graphical User Interface) interface for configuration, management and supervision. The design is cost-effective and has been successfully employed to verify several IP (Intellectual Property) blocks of our EOS chip. Moreover, it is flexible and can be applied as a general-purpose verification platform.

Scheduling Algorithm Based on Storage Capacity of Communication in Hardware/Software Integrated System

In this paper, the storage capacity of communication among cores and processors is taken into account and a maximum D-value-first algorithm is proposed. By improving the hardware parallelism in the task execution process, the maximum storage requirements for communication are minimized. Experimental results with various directed acyclic graph models showed that compared with the earliest-task-first algorithm, the storage requirements for communication were reduced by 22.46%, on average, while the average of makespan only increased by 0.82%,.

Hardware/software partitioning based on dynamic combination of maximum entropy and chaos optimization algorithm

This paper presents an algorithm that combines the chaos optimization algorithm with the maximum entropy ( COA-ME) by using entropy model based on chaos algorithm,in which the maximum entropy is used as the second method of searching the excellent solution. The search direction is improved by chaos optimization algorithm and realizes the selective acceptance of wrong solution. The experimental result shows that the presented algorithm can be used in the partitioning of hardware/software of reconfigurable system. It effectively reduces the local extremum problem,and search speed as well as performance of partitioning is improved.

A hardware/software co-optimization approach for embedded software of MP3 decoder

In order to improve the efficiency of embedded software running on processor core, this paper proposes a hard-ware/software co-optimization approach for embedded software from the system point of view. The proposed stepwise methods aim at exploiting the structure and the resources of the processor as much as possible for software algorithm optimization. To achieve low memory usage and low frequency need for the same performance, this co-optimization approach was used to optimize embedded software of MP3 decoder based on a 16-bit fixed-point DSP core. After the optimization, the results of decoding 128 kbps, 44.1 kHz stereo MP3 on DSP evaluation platform need 45.9 MIPS and 20.4 kbytes memory space. The optimization rate achieves 65.6% for memory and 49.6% for frequency respectively compared with the results by compiler using floating-point computation. The experimental result indicates the availability of the hardware/software co-optimization approach depending on the algorithm and architecture.

New Approach for Hardware/Software Embedded System Conception Based on the Use of Design Patterns

This paper deals with a new hardware/software embedded system design methodology based on design pattern approach by development of a new design tool called smartcell. Three main constraints of embedded systems design process are investigated: the complexity, the partitioning between hardware and software aspects and the reusability. Two intermediate models are carried out in order to solve the complexity problem. The partitioning problem deals with the proposed hardware/software partitioning algorithm based on Ant Colony Optimisation. The reusability problem is resolved by synthesis of intellectual property blocks. Specification and integration of an intelligent controller on heterogeneous platform are considered to illustrate the proposed approach.

TikTak: A Scalable Simulator of Wireless Sensor Networks Including Hardware/Software Interaction

We present a simulation framework for wireless sensor networks developed to allow the design exploration and the complete microprocessor-instruction-level debug of network formation, data congestion, nodes interaction, all in one simulation environment. A specifically innovative feature is the co-emulation of selected nodes at clock-cycle-accurate hardware processing level, allowing code debug and exact execution latency evaluation (considering both protocol stack and application), together with other nodes at abstract protocol level, meeting a designer’s needs of simulation speed, scalability and reliability. The simulator is centered on the Zigbee protocol and can be retargeted for different node micro-architectures.

Research on Software Radio Fuze

The functions and characteristics of software radio are discussed. Using techniques and method of software radio, the concept and advantages of a new kind of radio fuze, software radio fuze, are analysed. Several kinds of hardware platform structures of the software radio fuze are studied and the key techniques are analysed. The software radio fuze will become the most promising radio fuze techniques in 21st century.

Domain-Oriented Software Defined Computing Architecture

With the introduction of software defined hardware by DARPA Electronics Resurgence Initiative,software definition will be the basic attribute of information system.Benefiting from boundary certainty and algorithm aggregation of domain applications,domain-oriented computing architecture has become the technical direction that considers the high flexibility and efficiency of information system.Aiming at the characteristics of data-intensive computing in different scenarios such as Internet of Things(IoT),big data,artificial intelligence(AI),this paper presents a domain-oriented software defined computing architecture,discusses the hierarchical interconnection structure,hybrid granularity computing element and its computational kernel extraction method,finally proves the flexibility and high efficiency of this architecture by experimental comparison.

The Software Industry Promotes All-round Cooperation

Software can be seen almost everywhere and is now defining the world.Software has transitioned from an affiliate of hardware,to a network service that is present in every corner of our social lives.

System-on-a-Chip (SoC) Based Hardware Acceleration for Video Codec

Nowadays, from home monitoring to large airport security, a lot of digital video surveillance systems have been used. Digital surveillance system usually requires streaming video processing abilities. As an advanced video coding method, H.264 is introduced to reduce the large video data dramatically (usually by 70X or more). However, computational overhead occurs when coding and decoding H.264 video. In this paper, a System-on-a-Chip (SoC) based hardware acceleration solution for video codec is proposed, which can also be used for other software applications. The characteristics of the video codec are analyzed by using the profiling tool. The Hadamard function, which is the bottleneck of H.264, is identified not only by execution time but also another two attributes, such as cycle per loop and loop round. The Co-processor approach is applied to accelerate the Hadamard function by transforming it to hardware. Performance improvement, resource costs and energy consumption are compared and analyzed. Experimental results indicate that 76.5% energy deduction and 8.09X speedup can be reached after balancing these three key factors.

从ware到software

随着电子计算机的日益普及,今天在美国由—ware这个构词成分所组成的词屡屡可见。据美国哈佛大学的教育学教授 Howard Gardner声称,在近期召开的一次有关人工智能的学术会议之后,—ware词突然变得风靡起来。一位长期从事人类记忆研究的神经生物家甚至说,他觉得自已还不能适应这种情况,完全成了“a student of wetware among thecomputer hackers”(处在电子计算机专家中间一名学生)。从80年代初开始,wetware一词便被用来指 human brain。本来也可以用另外几个词:skullware,grayware(gray

虚拟现实技术在数字媒体交互中的应用

相比于传统媒体技术,数字媒体采用更多的先进技术,是信息量大、操作体验感好、支持用户更多的主动操作。虚拟现实技术可以提供良好的体验感、满意度、实时性,对于数字媒体技术交互过程的改变具有重要的意义。该文首先从硬件角度分析基于虚拟现实技术的数字媒体交互采用的设备,包括计算机设备、头盔、手套、手柄、运动捕捉、模拟驾驶和全息现实等。其次从软件角度分析基于虚拟现实技术的数字媒体交互的设计流程和框架,包括虚拟现实软件平台、模拟和交互软件、内容开发工具等软件环境的支持等。性能测试实验结果显示,基于虚拟现实的数字媒体交互过程设计,最终用户使用满意度达到95%以上,实时性提高12%以上。

通用信道编译码算法物理性能快速仿真系统

为实现信道编译码硬件算法物理性能的快速、准确验证,提出一种软硬件协同的通用化信道编译码算法物理性能快速仿真与性能评估系统。PC上位机软件主要实现模拟信源/噪声数据生成、仿真数据后分析、数据/控制指令传输以及与FPGA下位机交互等功能;FPGA下位机通过设计数据调度与系统控制、信道编译码算法架构、加噪信道以及数据统计等单元,构建通用编译码算法验证系统硬件系统架构,支持不同信道编译码算法物理性能的高效、准确验证。以系统当前支持的BCH码、LDPC码、删余卷积码、RS码及其串行级联码的性能仿真为例开展性能测试,性能恶化最大值低于0.4 dB,在10-7误码率统计量级下,仿真时间低于12 s,验证仿真评估系统的准确性、可靠性与有效性。系统采用的通用级联架构还可支持其他信道编译码算法的快速移植与部署,可为信道编译码算法物理性能快速验证提供一种有效的解决方案。

新能源汽车的驱动电机系统研究和设计

通过改变新能源汽车的能源消耗方式,能提高节能减排工作效果,促进新能源开发利用工作顺利进行,保证社会经济实现可持续发展。科学技术的发展决定着新能源汽车的研发进程,驱动电机系统作为新能源汽车的关键点,涉及新能源汽车研发的核心技术,相关人员要注重新能源汽车的驱动电机系统研究和设计,提高设计的合理性。

能源动力类别研究生产教融合联合培养基地建设模式与实践

培养出满足新时代要求的具有创新精神和实践能力的高水平能源动力类别研究生是我国早日实现“双碳”目标的迫切需求。构建产教融合联合培养基地,是深化产教融合、实现能源动力类别研究生教育高质量发展的关键环节。该文总结长安大学在能源动力类别(动力工程及电气工程)研究生培养中基于产教融合建设联合培养基地的模式及实践工作,提出软-硬件协同构建产教融合联合培养实践基地的理念,具体阐述该理念在动力工程及电气工程等能源动力类别研究生培养中的具体实践与应用,以期为能源动力类别研究生实践创新能力的培养提供参考。

基于PLC和调速装置的纸机能耗控制系统设计

为提高造纸机真空部的自动化控制水平,提升造纸企业的成本控制能力,基于PLC和真空度传感器等硬件对变频器功率实施控制,进而实现对水泵和真空泵的动态调整,使水流量和变频器功率维持在较低水平,降低造纸机干燥部运行能耗。为实现该系统的工业应用,提出了纸机能耗控制系统的主程序流程,同时采用WinCC(Windows Control Center,视窗控制中心)组态软件为上位机设计人机交互界面。该操作界面简洁美观、交互友好,可帮助车间工作人员实时掌握纸机真空部运行数据,合理调整真空部变频器运行功率,实现低能耗生产。

空间信息与数字技术专业实践教学模式探讨

以培养高素质的空间信息与数字技术专业人才为目标,针对空间信息综合实践教学,结合空间信息科学专业知识面广、系统性强、与工程结合紧密和新技术发展迅速等特点,设计了层次化的人才培养模式,构筑了由综合设计实验层和创新实验层构成的双层实验实践教学体系。采用软件仿真与阶段实物实践相融合的实验教学模式,培养学生理论与实践紧密结合的综合能力,并能够运用辩证思维,分析科学问题和工程实际问题,从而培养学生科学思维和解决复杂工程问题的能力。

“数字电路与逻辑设计”课程改革与实践

针对“数字电路与逻辑设计”课程教学过程存在的问题,以培养学生系统设计能力、软硬件协同设计和调试能力为目标,完善教学大纲和课件,建设“学习通”线上课程教学资源,采取线上线下混合教学模式,制作微课视频和课程案例库,增加课程大作业,重新修订实验指导书,采取多元化的考核和评价体系。实践表明,课程改革实施效果较好,提高了学生工程实践能力,兼顾了基础和系统的人才培养导向。