Design of a high performance track and hold （T/H） circuit for high-resolution high-speed analog-to-digital converter （ADC） is presented, which has been implemented in 0.18 μm CMOS process. An improved bootstrappe...Design of a high performance track and hold （T/H） circuit for high-resolution high-speed analog-to-digital converter （ADC） is presented, which has been implemented in 0.18 μm CMOS process. An improved bootstrapped and bulk-switching technique is introduced to greatly minimize the nonlinearity of sampling network over a wide bandwidth, and the addition of a modified pre-charge circuit helps reducing the total power consumption. The experimental results show that the proposed T/H circuit achieves over 77 dB SFDR （spurious-free dynamic range） and 70 dB THD （total harmonic distortion） at 100 MHz sampling rate and maintains the performance with input frequency up to 305 MHz while consuming 47 mW power.展开更多
A simulation code that executes the tracking of longitudinal oscillations of the bunches for the double rf system of the Hefei Light Source Ⅱ Project （HLS-Ⅱ） is presented to estimate the mean beam lifetime and the...A simulation code that executes the tracking of longitudinal oscillations of the bunches for the double rf system of the Hefei Light Source Ⅱ Project （HLS-Ⅱ） is presented to estimate the mean beam lifetime and the Robinson instabilities. The tracking results show that the mean beam lifetime is in agreement with the analytical results and the system is stable when we tune the harmonic cavity in the optimum lengthening conditions. Moreover, the simulated results of the asymmetric fill pattern show that some bunches are compressed only with a 7% gap （3 gaps）, which will lead to the reduction in the mean bunch lengthening and potential beam lifetime. It is demonstrated that HLS-Ⅱ with a passive higher harmonic cavity is not suitable for operating in an asymmetric fill pattern.展开更多
文摘Design of a high performance track and hold （T/H） circuit for high-resolution high-speed analog-to-digital converter （ADC） is presented, which has been implemented in 0.18 μm CMOS process. An improved bootstrapped and bulk-switching technique is introduced to greatly minimize the nonlinearity of sampling network over a wide bandwidth, and the addition of a modified pre-charge circuit helps reducing the total power consumption. The experimental results show that the proposed T/H circuit achieves over 77 dB SFDR （spurious-free dynamic range） and 70 dB THD （total harmonic distortion） at 100 MHz sampling rate and maintains the performance with input frequency up to 305 MHz while consuming 47 mW power.
基金Supported by National Natural Science Foundation of China(10675116)Major State Basic Research Development Programme of China(2011CB808301)
文摘A simulation code that executes the tracking of longitudinal oscillations of the bunches for the double rf system of the Hefei Light Source Ⅱ Project （HLS-Ⅱ） is presented to estimate the mean beam lifetime and the Robinson instabilities. The tracking results show that the mean beam lifetime is in agreement with the analytical results and the system is stable when we tune the harmonic cavity in the optimum lengthening conditions. Moreover, the simulated results of the asymmetric fill pattern show that some bunches are compressed only with a 7% gap （3 gaps）, which will lead to the reduction in the mean bunch lengthening and potential beam lifetime. It is demonstrated that HLS-Ⅱ with a passive higher harmonic cavity is not suitable for operating in an asymmetric fill pattern.
