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Physical Implementation of the Eight-Core Godson-3B Microprocessor
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作者 王茹 范宝峡 +7 位作者 杨梁 高燕萍 刘动 肖斌 王江嵋 张译夫 王宏 胡伟武 《Journal of Computer Science & Technology》 SCIE EI CSCD 2011年第3期520-527,共8页
The Godson-3B processor is a powerful processor designed for high performance servers including Dawning Servers. It offers significantly improved performance over previous Godson-3 series CPUs by incorporating eight C... The Godson-3B processor is a powerful processor designed for high performance servers including Dawning Servers. It offers significantly improved performance over previous Godson-3 series CPUs by incorporating eight CPU cores and vector computing units. It contains 582.6 M transistors within 300 mm2 area in 65 nm technology and is implemented in parallel with full hierarchical design flows. In Godson-3B, advanced clock distribution mechanisms including GALS (Globally Asynchronous Locally Synchronous) and clock mesh are adopted to obtain an OCV tolerable clock network. Custom-designed de-skew modules are also implemented to afford further latency balance after fabrication. The power reduction of Godson- 3B is maintained by MLMM (Multi Level Multi Mode) clock gating and multi-threshold-voltage cells substitution schemes. The highest frequency of Godson-3B is 1.05 GHz and the peak performance is 128 GFlops (double-precision) or 256 GFlops (single-precision) with 40 W power consumption. 展开更多
关键词 physical implementation hierarchical design flow GALS clock mesh low power
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A Robust and Power-Effcient SoC Implementation in 65nm
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作者 肖斌 张译夫 +3 位作者 高燕萍 杨梁 吴冬梅 范宝峡 《Journal of Computer Science & Technology》 SCIE EI CSCD 2013年第4期682-688,共7页
Godson2H is a complex SoC (System-on-Chip) of Godson series, which is a 117mm2, 152 million transistors chip fabricated in 65 nm CMOS LP/GP process technology. It integrates a 1 GHz processor core and abundant high ... Godson2H is a complex SoC (System-on-Chip) of Godson series, which is a 117mm2, 152 million transistors chip fabricated in 65 nm CMOS LP/GP process technology. It integrates a 1 GHz processor core and abundant high or low speed peripheral IO interfaces. To overcome on-chip-variation problems in deep submicron designs, many methods are adopted in clock tree, and PVT detectors are integrated for debug. To meet the low power constraints in different applications, most of state-of-the-art low power methods are used carefully, such as dynamic voltage and frequency scaling, power gating and aggressive multi-voltage design. 展开更多
关键词 SYSTEM-ON-CHIP on-chip-variation PVT detector low power hierarchical design flow
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