针对传统无源有损积分环路滤波器相较于有源无损积分环路滤波器,具有功耗低、电路设计简单等特点,但其噪声传输函数(NTF:Noise Transfer Function)平滑,噪声整形效果较弱的问题,提出了一种无源无损的二阶积分环路滤波器,保留了无源有损...针对传统无源有损积分环路滤波器相较于有源无损积分环路滤波器,具有功耗低、电路设计简单等特点,但其噪声传输函数(NTF:Noise Transfer Function)平滑,噪声整形效果较弱的问题,提出了一种无源无损的二阶积分环路滤波器,保留了无源有损积分优点的同时具有良好噪声整形效果。设计了一款分辨率为16 bit、采样率为2 Ms/s的混合架构噪声整形SAR ADC。仿真结果表明,在125 kHz带宽、过采样比为8时,实现了高信号与噪声失真比(SNDR(Signal to Noise and Distortion Ratio)为91.1 dB)、高精度(14.84 bit)和低功耗(285μW)的性能。展开更多
目的探讨以增强T2-FLAIR序列为参照测量近瘤周水肿区的ADC值及rADC值鉴别脑内转移瘤及高级别胶质瘤的价值;方法收集行常规T1增强及T2-FLAIR增强和DWI检查的高级别胶质瘤34例与30例脑转移瘤,将瘤周10mm范围内作为感兴趣区(regions of int...目的探讨以增强T2-FLAIR序列为参照测量近瘤周水肿区的ADC值及rADC值鉴别脑内转移瘤及高级别胶质瘤的价值;方法收集行常规T1增强及T2-FLAIR增强和DWI检查的高级别胶质瘤34例与30例脑转移瘤,将瘤周10mm范围内作为感兴趣区(regions of interest,ROI)测量ADC值,并计算相应的rADC值。结果脑转移瘤的瘤周水肿带的ADC值(1.83×10^(-3)±0.13)×10^(-2)mm^(2)/s及rADC值(2.39×10^(-3)±0.21)×10^(-2)mm^(2)/s;高级别胶质瘤瘤周水肿区ADC值(1.35×10^(-3)±0.16)×10^(-2)mm^(2)/s及rADC值(1.83×10^(-3)±0.13)×10^(-2)mm^(2)/s,差异有统计学意义(P<0.05);结论以T2-FLAI R增强序列为参照测量高级别胶质瘤及脑转移瘤的瘤周水肿的ADC值及rADC值能有效鉴别两种肿瘤。展开更多
A high speed column-parallel CDS/ADC circuit with nonlinearity compensation is proposed in this paper.The correlated double sampling (CDS) and analog-to-digital converter (ADC) functions are integrated in a threephase...A high speed column-parallel CDS/ADC circuit with nonlinearity compensation is proposed in this paper.The correlated double sampling (CDS) and analog-to-digital converter (ADC) functions are integrated in a threephase column-parallel circuit based on two floating gate inverters and switched-capacitor network.The conversion rate of traditional single-slope ADC is speeded up by dividing quantization to coarse step and fine step.A storage capacitor is used to store the result of coarse step and locate the section of ramp signal of fine step,which can reduce the clock step from 2 n to 2 (n/2+1).The floating gate inverters are implemented to reduce the power consumption.Its induced nonlinear offset is cancelled by introducing a compensation module to the input of inverter,which can equalize the coupling path in three phases of the proposed circuit.This circuit is designed and simulated for CMOS image sensor with 640×480 pixel array using Chartered 0.18μm process.Simulation results indicate that the resolution can reach 10-bit and the maximum frame rate can reach 200 frames/s with a main clock of 10MHz.The power consumption of this circuit is less than 36.5μW with a 3.3V power supply.The proposed CDS/ADC circuit is suitable for high resolution and high speed image sensors.展开更多
由于γ射线对SiO_(2)的电离作用,会引起MOS管阈值电压负漂移和二极管死区漏电变化,负漂移和漏电变化程度随MOS管栅氧厚度增加而加大。这样在设计高压直采ADC时,实现稳定基准和低漏电开关是个难点,通常的解决方法是优化电路参数裕量和版...由于γ射线对SiO_(2)的电离作用,会引起MOS管阈值电压负漂移和二极管死区漏电变化,负漂移和漏电变化程度随MOS管栅氧厚度增加而加大。这样在设计高压直采ADC时,实现稳定基准和低漏电开关是个难点,通常的解决方法是优化电路参数裕量和版图,但很少考虑MOS管的反型和二极管的死区漏电。重点研究了MOS器件阈值和二极管死区漏电流变化对器件参数影响的机理,并提出一种不同电源电压MOS管结合设计思路,同时考虑了减小二极管死区漏电的影响。最后,通过使用不同电源电压MOS管设计和二极管死区漏电流分析,高压ADC在50 k rad(Si)总剂量条件下仍能达到设计要求。展开更多
设计实现了一种带参考通道的时间交叉ADC(TIADC)通道误差数字后台实时校准方法。参考通道ADC与TIADC各个子通道ADC依次对齐,对同一输入信号在同一时刻进行采样并转换,输出差值被用在数字后台LMS自适应校准算法中以计算通道间的失配误差...设计实现了一种带参考通道的时间交叉ADC(TIADC)通道误差数字后台实时校准方法。参考通道ADC与TIADC各个子通道ADC依次对齐,对同一输入信号在同一时刻进行采样并转换,输出差值被用在数字后台LMS自适应校准算法中以计算通道间的失配误差估计值,实现对各通道失调失配、增益失配和采样时刻失配造成误差的实时校准。FPGA实验结果表明,应用于12 bit,4通道,采样频率400 MS/s的TIADC中,归一化输入频率fin/fs=0.134时,在失调误差、增益误差和采样时钟误差分别为5%FSR、5%和1%Ts条件下,校准后信号噪声失真比(SNR)和无杂散动态范围(SFDR)分别提高了约19.61 d B和28.28 d B,为73.83 d B和86.15 d B,有效位达到11.96位。本校准方法计算复杂度低、易于硬件实现,能够应用于任意通道数的TIADC校准。展开更多
文摘针对传统无源有损积分环路滤波器相较于有源无损积分环路滤波器,具有功耗低、电路设计简单等特点,但其噪声传输函数(NTF:Noise Transfer Function)平滑,噪声整形效果较弱的问题,提出了一种无源无损的二阶积分环路滤波器,保留了无源有损积分优点的同时具有良好噪声整形效果。设计了一款分辨率为16 bit、采样率为2 Ms/s的混合架构噪声整形SAR ADC。仿真结果表明,在125 kHz带宽、过采样比为8时,实现了高信号与噪声失真比(SNDR(Signal to Noise and Distortion Ratio)为91.1 dB)、高精度(14.84 bit)和低功耗(285μW)的性能。
文摘目的探讨以增强T2-FLAIR序列为参照测量近瘤周水肿区的ADC值及rADC值鉴别脑内转移瘤及高级别胶质瘤的价值;方法收集行常规T1增强及T2-FLAIR增强和DWI检查的高级别胶质瘤34例与30例脑转移瘤,将瘤周10mm范围内作为感兴趣区(regions of interest,ROI)测量ADC值,并计算相应的rADC值。结果脑转移瘤的瘤周水肿带的ADC值(1.83×10^(-3)±0.13)×10^(-2)mm^(2)/s及rADC值(2.39×10^(-3)±0.21)×10^(-2)mm^(2)/s;高级别胶质瘤瘤周水肿区ADC值(1.35×10^(-3)±0.16)×10^(-2)mm^(2)/s及rADC值(1.83×10^(-3)±0.13)×10^(-2)mm^(2)/s,差异有统计学意义(P<0.05);结论以T2-FLAI R增强序列为参照测量高级别胶质瘤及脑转移瘤的瘤周水肿的ADC值及rADC值能有效鉴别两种肿瘤。
基金Supported by National Natural Science Foundation of China (No.60806010,No.60976030)
文摘A high speed column-parallel CDS/ADC circuit with nonlinearity compensation is proposed in this paper.The correlated double sampling (CDS) and analog-to-digital converter (ADC) functions are integrated in a threephase column-parallel circuit based on two floating gate inverters and switched-capacitor network.The conversion rate of traditional single-slope ADC is speeded up by dividing quantization to coarse step and fine step.A storage capacitor is used to store the result of coarse step and locate the section of ramp signal of fine step,which can reduce the clock step from 2 n to 2 (n/2+1).The floating gate inverters are implemented to reduce the power consumption.Its induced nonlinear offset is cancelled by introducing a compensation module to the input of inverter,which can equalize the coupling path in three phases of the proposed circuit.This circuit is designed and simulated for CMOS image sensor with 640×480 pixel array using Chartered 0.18μm process.Simulation results indicate that the resolution can reach 10-bit and the maximum frame rate can reach 200 frames/s with a main clock of 10MHz.The power consumption of this circuit is less than 36.5μW with a 3.3V power supply.The proposed CDS/ADC circuit is suitable for high resolution and high speed image sensors.
文摘由于γ射线对SiO_(2)的电离作用,会引起MOS管阈值电压负漂移和二极管死区漏电变化,负漂移和漏电变化程度随MOS管栅氧厚度增加而加大。这样在设计高压直采ADC时,实现稳定基准和低漏电开关是个难点,通常的解决方法是优化电路参数裕量和版图,但很少考虑MOS管的反型和二极管的死区漏电。重点研究了MOS器件阈值和二极管死区漏电流变化对器件参数影响的机理,并提出一种不同电源电压MOS管结合设计思路,同时考虑了减小二极管死区漏电的影响。最后,通过使用不同电源电压MOS管设计和二极管死区漏电流分析,高压ADC在50 k rad(Si)总剂量条件下仍能达到设计要求。
文摘设计实现了一种带参考通道的时间交叉ADC(TIADC)通道误差数字后台实时校准方法。参考通道ADC与TIADC各个子通道ADC依次对齐,对同一输入信号在同一时刻进行采样并转换,输出差值被用在数字后台LMS自适应校准算法中以计算通道间的失配误差估计值,实现对各通道失调失配、增益失配和采样时刻失配造成误差的实时校准。FPGA实验结果表明,应用于12 bit,4通道,采样频率400 MS/s的TIADC中,归一化输入频率fin/fs=0.134时,在失调误差、增益误差和采样时钟误差分别为5%FSR、5%和1%Ts条件下,校准后信号噪声失真比(SNR)和无杂散动态范围(SFDR)分别提高了约19.61 d B和28.28 d B,为73.83 d B和86.15 d B,有效位达到11.96位。本校准方法计算复杂度低、易于硬件实现,能够应用于任意通道数的TIADC校准。
