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Gate Current for MOSFETs with High k Dielectric Materials 被引量:2
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作者 刘晓彦 康晋锋 韩汝琦 《Journal of Semiconductors》 EI CAS CSCD 北大核心 2002年第10期1009-1013,共5页
The MOSFET gate currents of high k gate dielectrics due to direct tunneling are investigated by using a new direct tunneling current model developed.The model includes both the inversion layer quantization effect with... The MOSFET gate currents of high k gate dielectrics due to direct tunneling are investigated by using a new direct tunneling current model developed.The model includes both the inversion layer quantization effect with finite barrier height and the polysilicon depletion effect.The impacts of dielectric constant and conduction band offset as well as the band gap on the gate current are discussed.The results indicate that the gate dielectric materials with higher dielectric constant,larger conduction band offset and the larger band gap are necessary to reduce the gate current.The calculated results can be used as a guide to select the appropriate high k gate dielectric materials for MOSFETs. 展开更多
关键词 MOSFET direct tunneling gate current high k gate dielectric
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Energy-band alignment of atomic layer deposited(HfO_2)_x(Al_2O_3)_(1-x) gate dielectrics on 4H-SiC
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作者 贾仁需 董林鹏 +5 位作者 钮应喜 李诚瞻 宋庆文 汤晓燕 杨霏 张玉明 《Chinese Physics B》 SCIE EI CAS CSCD 2015年第3期408-411,共4页
We study a series of(HfO2)x(Al2O3)1-x /4H-SiC MOS capacitors. It is shown that the conduction band offset of HfO2 is 0.5 e V and the conduction band offset of Hf AlO is 1.11–1.72 e V. The conduction band offsets... We study a series of(HfO2)x(Al2O3)1-x /4H-SiC MOS capacitors. It is shown that the conduction band offset of HfO2 is 0.5 e V and the conduction band offset of Hf AlO is 1.11–1.72 e V. The conduction band offsets of(Hf O2)x(Al2O3)1-x are increased with the increase of the Al composition, and the(HfO2)x(Al2O3)1-x offer acceptable barrier heights(〉 1 e V)for both electrons and holes. With a higher conduction band offset,(Hf O2)x(Al2O3)1-x/4H-SiC MOS capacitors result in a ~ 3 orders of magnitude lower gate leakage current at an effective electric field of 15 MV/cm and roughly the same effective breakdown field of ~ 25 MV/cm compared to HfO2. Considering the tradeoff among the band gap, the band offset, and the dielectric constant, we conclude that the optimum Al2O3 concentration is about 30% for an alternative gate dielectric in 4H-Si C power MOS-based transistors. 展开更多
关键词 energy-band alignment high k gate dielectrics 4H-SiC MOS capacitor
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Analytical modeling of the direct tunneling current through high-k gate stacks for long-channel cylindrical surrounding-gate MOSFETs 被引量:1
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作者 石利娜 庄奕琪 +1 位作者 李聪 李德昌 《Journal of Semiconductors》 EI CAS CSCD 2014年第3期64-69,共6页
An analytical direct tunneling gate current model for cylindrical surrounding gate(CSG) MOSFETs with high-k gate stacks is developed. It is found that the direct tunneling gate current is a strong function of the g... An analytical direct tunneling gate current model for cylindrical surrounding gate(CSG) MOSFETs with high-k gate stacks is developed. It is found that the direct tunneling gate current is a strong function of the gate's oxide thickness, but that it is less affected by the change in channel radius. It is also revealed that when the thickness of the equivalent oxide is constant, the thinner the first layer, the smaller the direct tunneling gate current.Moreover, it can be seen that the dielectric with a higher dielectric constant shows a lower tunneling current than expected. The accuracy of the analytical model is verified by the good agreement of its results with those obtained by the three-dimensional numerical device simulator ISE. 展开更多
关键词 direct tunneling gate current high dielectric gate stacks cylindrical surrounding gate MOSFETs
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Challenges of Process Technology in 32nm Technology Node 被引量:1
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作者 吴汉明 王国华 +1 位作者 黄如 王阳元 《Journal of Semiconductors》 EI CAS CSCD 北大核心 2008年第9期1637-1653,共17页
According to the international technology roadmap for semiconductors (ITRS),32nm technology node will be introduced around 2009. Scaling of CMOS logic devices from 45 to 32nm node has come across significant barrier... According to the international technology roadmap for semiconductors (ITRS),32nm technology node will be introduced around 2009. Scaling of CMOS logic devices from 45 to 32nm node has come across significant barriers. Overcoming these pitch-scaling induced barriers requires integrating the most advanced process technologies into product manufacturing. This paper reviews and discusses new technology applications that could be potentially integrated into 32nm node in the following areas:extension of immersion lithography,mobility enhancement substrate technology,metal/ high-k (MHK) gate stack, ultra-shallow junction (USJ) and other strain enhancement engineering methods, including stress proximity effect (SPT), dual stress liner (DSL), stress memorization technique (SMT), high aspect ratio process (HARP) for STI and PMD,embedded SiGe (for pFET) and SiC (for nFET) source/drain (S/D) using selective epitaxial growth (SEG) method,metallization for middle of line (MOL) and back-end of line (BEOL) ,and ultra low-k (ULK) integration. 展开更多
关键词 CMOS technology 32nm technology node mobility enhancement metal gate/high k dielectrics ultra low k dielectrics
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