A review of rare-earth oxide films as high k dielectrics in MOS devices——Commemorating the 100th anniversary of the birth of Academician Guangxian Xu

Recently,rare-earth oxide films have attracted more and more attention as gate dielectrics in metaloxide-semiconductor(MOS)devices,showing the advantages of high dielectric constant(k value),large band gap(Eg)and outstanding physical and chemical stability in contact with silicon substrates.This paper reviews the recent development of rare earth oxide-based gate dielectric films.Aiming at the problem that k value of rare earth oxides(REOs)is generally inversely proportio nal to the band gap value,one of the biggest technical obstacles of high k films,we reviewed three strategies reported in recent papers,namely doping modification,nitriding treatment and multilayer composite,which can provide some insights for long-term development of MOS devices in integrated circuit(IC).

Gate Current for MOSFETs with High k Dielectric Materials

The MOSFET gate currents of high k gate dielectrics due to direct tunneling are investigated by using a new direct tunneling current model developed.The model includes both the inversion layer quantization effect with finite barrier height and the polysilicon depletion effect.The impacts of dielectric constant and conduction band offset as well as the band gap on the gate current are discussed.The results indicate that the gate dielectric materials with higher dielectric constant,larger conduction band offset and the larger band gap are necessary to reduce the gate current.The calculated results can be used as a guide to select the appropriate high k gate dielectric materials for MOSFETs.

Designing high k dielectric films with LiPON-Al_(2)O_(3)hybrid structure by atomic layer deposition

A large amount of ultra-low-power consumption electronic devices are urgently needed in the new era of the internet of things,which demand relatively low frequency response.Here,atomic layer deposition has been utilized to fabricate the ion polarization dielectric of the Li PON-Al_(2)O_(3) hybrid structure.The Li PON thin film is periodically stacked in the Al_(2)O_(3) matrix.This hybrid structure presents a frequency-dependent dielectric constant,of which k is significantly higher than the aluminum oxide matrix from 1 k Hz to 200 k Hz in frequency.The increased dielectric constant is attributed to the lithium ions shifting locally upon the applied electrical field,which shows an additional polarization to the Al_(2)O_(3) matrix.This work provides a new strategy with promising potential to engineers for the dielectric constant of the gate oxide and sheds light on the application of electrolyte/dielectric hybrid structure in a variety of devices from capacitors to transistors.

Energy-band alignment of atomic layer deposited(HfO_2)_x(Al_2O_3)_(1-x) gate dielectrics on 4H-SiC

We study a series of（HfO2）x（Al2O3）1-x /4H-SiC MOS capacitors. It is shown that the conduction band offset of HfO2 is 0.5 e V and the conduction band offset of Hf AlO is 1.11–1.72 e V. The conduction band offsets of（Hf O2）x（Al2O3）1-x are increased with the increase of the Al composition, and the（HfO2）x（Al2O3）1-x offer acceptable barrier heights（〉 1 e V）for both electrons and holes. With a higher conduction band offset,（Hf O2）x（Al2O3）1-x/4H-SiC MOS capacitors result in a ～ 3 orders of magnitude lower gate leakage current at an effective electric field of 15 MV/cm and roughly the same effective breakdown field of ～ 25 MV/cm compared to HfO2. Considering the tradeoff among the band gap, the band offset, and the dielectric constant, we conclude that the optimum Al2O3 concentration is about 30% for an alternative gate dielectric in 4H-Si C power MOS-based transistors.

Challenges of Process Technology in 32nm Technology Node

According to the international technology roadmap for semiconductors （ITRS）,32nm technology node will be introduced around 2009. Scaling of CMOS logic devices from 45 to 32nm node has come across significant barriers. Overcoming these pitch-scaling induced barriers requires integrating the most advanced process technologies into product manufacturing. This paper reviews and discusses new technology applications that could be potentially integrated into 32nm node in the following areas：extension of immersion lithography,mobility enhancement substrate technology,metal/ high-k （MHK） gate stack, ultra-shallow junction （USJ） and other strain enhancement engineering methods, including stress proximity effect （SPT）, dual stress liner （DSL）, stress memorization technique （SMT）, high aspect ratio process （HARP） for STI and PMD,embedded SiGe （for pFET） and SiC （for nFET） source/drain （S/D） using selective epitaxial growth （SEG） method,metallization for middle of line （MOL） and back-end of line （BEOL） ,and ultra low-k （ULK） integration.

Selective wet etch of a TaN metal gate with an amorphous-silicon hard mask

The appropriate wet etch process for the selective removal of TaN on the HfSiON dielectric with an amorphous-silicon（a-Si） hardmask is presented.SCI（NH4OH：H2O2：H2O）,which can achieve reasonable etch rates for metal gates and very high selectivity to high-k dielectrics and hardmask materials,is chosen as the TaN etchant. Compared with the photoresist mask and the tetraethyl orthosilicate（TEOS） hardmask,the a-Si hardmask is a better choice to achieve selective removal of TaN on the HfSiON dielectric because it is impervious to the SC1 etchant and can be readily etched with NH4OH solution without attacking the TaN and the HfSiON film.In addition,the surface of the HfSiON dielectric is smooth after the wet etching of the TaN metal gate and a-Si hardmask removal,which could prevent device performance degradation.Therefore,the wet etching of TaN with the a-Si hardmask can be applied to dual metal gate integration for the selective removal of the first TaN metal gate deposition.

TaN wet etch for application in dual-metal-gate integration technology

Wet-etch etchants and the TaN film method for dual-metal-gate integration are investigated. Both HF/HN O3/H2O and NH4OH/H2O2 solutions can etch TaN effectively, but poor selectivity to the gate dielectric for the HF/HNO3/H2O solution due to HF being included in HF/HNO3/H2O, and the fact that TaN is difficult to etch in the NH4OH/H2O2 solution at the first stage due to the thin TaOxNy layer on the TaN surface, mean that they are difficult to individually apply to dual-metal-gate integration. A two-step wet etching strategy using the HF/HNO3/H2O solution first and the NH4OH/H2O2 solution later can fully remove thin TaN film with a photo-resist mask and has high selectivity to the HfSiON dielectric film underneath. High-k dielectric film surfaces are smooth after wet etching of the TaN metal gate and MOSCAPs show well-behaved C-V and Jg-Vg characteristics, which all prove that the wet etching of TaN has little impact on electrical performance and can be applied to dual-metal-gate integration technology for removing the first TaN metal gate in the PMOS region.