The decreasing feature sizes in complementary metal-oxide semiconductor (CMOS) transistor technology will require the replacement of SiO2 with gate dielectrics that have a high dielectric constant (high-k) because...The decreasing feature sizes in complementary metal-oxide semiconductor (CMOS) transistor technology will require the replacement of SiO2 with gate dielectrics that have a high dielectric constant (high-k) because as the SiO2 gate thickness is reduced below 1.4 nm, electron tunnelling effects and high leakage currents occur in SiO2, which present serious obstacles to future device reliability. In recent years significant progress has been made on the screening and selection of high-k gate dielectrics, understanding their physical properties, and their integration into CMOS technology. Now the family of hafnium oxide-based materials has emerged as the leading candidate for high-k gate dielectrics due to their excellent physical properties. It is also realized that the high-k oxides must be implemented in conjunction with metal gate electrodes to get sufficient potential for CMOS continue scaling. In the advanced nanoscale Si-based CMOS devices, the composition and thickness of interfacial layers in the gate stacks determine the critical performance of devices. Therefore, detailed atomic- scale understandings of the microstructures and interfacial structures built in the advanced CMOS gate stacks, are highly required. In this paper, several high-resolution electron, ion, and photon-based techniques currently used to characterize the high-k gate dielectrics and interfaces at atomic-scale, are reviewed. Particularly, we critically review the research progress on the characterization of interface behavior and structural evolution in the high-k gate dielectrics by high-resolution transmission electron microscopy (HRTEM) and the related techniques based on scanning transmission electron microscopy (STEM), including high-angle annular dark- field (HAADF) imaging (also known as Z-contrast imaging), electron energy-loss spectroscopy (EELS), and energy dispersive X-ray spectroscopy (EDS), due to that HRTEM and STEM have become essential metrology tools for characterizing the dielectric gate stacks in the present and future generations of CMOS devices. In Section 1 of this review, the working principles of each technique are briefly introduced and their key features are outlined. In Section 2, microstructural characterizations of high-k gate dielectrics at atomic-scale by electron microscopy are critically reviewed by citing some recent results reported on high-k gate dielectrics. In Section 3, metal gate electrodes and the interfacial structures between high-k dielectrics and metal gates are discussed. The electron beam damage effects in high-k gate stacks are also evaluated, and their origins and prevention are described in Section 4. Finally, we end this review with personal perspectives towards the future challenges of atomic-scale material characterization in advanced CMOS gate stacks.展开更多
Based on the elastic trap-assisted tunneling mechanism in high-κgate stacks,a quantum percolation tunneling current 1/fγ noise model is proposed by incorporating quantum tunneling theory into the quantum percolation...Based on the elastic trap-assisted tunneling mechanism in high-κgate stacks,a quantum percolation tunneling current 1/fγ noise model is proposed by incorporating quantum tunneling theory into the quantum percolation model.We conclude that the noise amplitude of the PSD(Power Spectral Density)for three stages,namely the fresh device,one-layer BD(breakdown),and two-layer BD,increases from 10-22→10-14→10-8 A2/Hz.Meanwhile,the noise exponent γ for the three stages,has the 1/f2type(γ→2),1/fγ type(γ→1~2),and 1/f type(γ→1),respectively.The simulation results are in good agreement with the experimental results.This model reasonably interprets the correlation between the bi-layer breakdown and the tunneling 1/fγ noise amplitude dependence and 1/fγ noise exponent dependence.These results provide a theoretical basis for the high-κ gate stacks bi-layer breakdown noise characterization methods.展开更多
Higher-s dielectric LaLuO3, deposited by molecular beam deposition, with TiN as gate stack is integrated into high-mobility Si/SiGe/SOI quantum-well p-type metal-oxide-semiconduetor field effect transistors. Threshold...Higher-s dielectric LaLuO3, deposited by molecular beam deposition, with TiN as gate stack is integrated into high-mobility Si/SiGe/SOI quantum-well p-type metal-oxide-semiconduetor field effect transistors. Threshold voltage shift and capacitance equivalent thickness shrink are observed, resulting from oxygen scavenging effect in LaLuO3 with ti-rich TiN after high temperature annealing. The mechanism of oxygen scavenging and its potential for resistive memory applications are analyzed and discussed.展开更多
Based on the exact resultant solution of two-dimensional Poisson's equation, the novel two-dimensional models, which include surface potential, threshold voltage, subthreshold current and subthreshold swing, have bee...Based on the exact resultant solution of two-dimensional Poisson's equation, the novel two-dimensional models, which include surface potential, threshold voltage, subthreshold current and subthreshold swing, have been developed for gate stack symmetrical double-gate strained-Si MOSFETs. The models are verified by numerical simulation. Besides offering the physical insight into device physics, the model provides the basic designing guidance of further immunity of short channel effect of complementary metal-oxide-semiconductor (CMOS)-based device in a nanoscale regime.展开更多
Gd2O3 thin films as high-κ gate dielectrics were deposited directly on Si(001) substrates by magnetron sputtering at a pressure of 1.3 Pa and different temperatures. X-ray diffraction results revealed that all the ...Gd2O3 thin films as high-κ gate dielectrics were deposited directly on Si(001) substrates by magnetron sputtering at a pressure of 1.3 Pa and different temperatures. X-ray diffraction results revealed that all the films grown from 450 to 570 ℃ were crystalline, and the Gd2O3 thin films consisted of a mixture of cubic and monoclinic phases. The growth temperature was a critical parameter for the phase constituents and their relative amount. Low temperature was favorable for the formation of cubic phase while higher temperature gave rise to more monoclinic phase. All the Gd2O3 thin films grown from different temperatures exhibited acceptable electrical properties, such as low leakage current density (JL) of 10-5 A/cm^2 at zero bias with capacitance equivalent SiO2 thickness in the range of 6-13 nm. Through the comparison between films grown at 450 and 570 ℃, the existence of monoclinic phase caused an increase in JL by nearly one order of magnitude and a reduction of effective dielectric constant from 17 to 9.展开更多
High-k gate dielectric Hf Ti ON Ga As metal-oxide–semiconductor(MOS) capacitors with La ON as interfacial passivation layer(IPL) and NH3- or N2-plasma surface pretreatment are fabricated, and their interfacial an...High-k gate dielectric Hf Ti ON Ga As metal-oxide–semiconductor(MOS) capacitors with La ON as interfacial passivation layer(IPL) and NH3- or N2-plasma surface pretreatment are fabricated, and their interfacial and electrical properties are investigated and compared with their counterparts that have neither La ON IPL nor surface treatment. It is found that good interface quality and excellent electrical properties can be achieved for a NH3-plasma pretreated Ga As MOS device with a stacked gate dielectric of Hf Ti ON/La ON. These improvements should be ascribed to the fact that the NH3-plasma can provide H atoms and NH radicals that can effectively remove defective Ga/As oxides. In addition, La ON IPL can further block oxygen atoms from being in-diffused, and Ga and As atoms from being out-diffused from the substrate to the high-k dielectric. This greatly suppresses the formation of Ga/As native oxides and gives rise to an excellent high-k/Ga As interface.展开更多
In the present work, a two-dimensional(2D) analytical framework of triple material symmetrical gate stack(TMGS)DG-MOSFET is presented in order to subdue the short channel effects. A lightly doped channel along wit...In the present work, a two-dimensional(2D) analytical framework of triple material symmetrical gate stack(TMGS)DG-MOSFET is presented in order to subdue the short channel effects. A lightly doped channel along with triple material gate having different work functions and symmetrical gate stack structure, showcases substantial betterment in quashing short channel effects to a good extent. The device functioning amends in terms of improved exemption to threshold voltage roll-off, thereby suppressing the short channel effects. The encroachments of respective device arguments on the threshold voltage of the proposed structure are examined in detail. The significant outcomes are compared with the numerical simulation data obtained by using 2D ATLAS;device simulator to affirm and formalize the proposed device structure.展开更多
The fringing-induced barrier lowering(FIBL) effect of sub-100 nm MOSFETs with high-k gate dielectrics is investigated using a two-dimensional device simulator.An equivalent capacitance theory is proposed to explain ...The fringing-induced barrier lowering(FIBL) effect of sub-100 nm MOSFETs with high-k gate dielectrics is investigated using a two-dimensional device simulator.An equivalent capacitance theory is proposed to explain the physics mechanism of the FIBL effect.The FIBL effect is enhanced and the short channel performance is degraded with increasing capacitance.Based on equivalent capacitance theory,the influences of channel length,junction depth,gate/lightly doped drain(LDD) overlap length,spacer material and spacer width on FIBL is thoroughly investigated.A stack gate dielectric is presented to suppress the FIBL effect.展开更多
The key technologies for the dual high-k and dual metal gate, such as the electrical optimization of metal insert poly-Si stack structure, the separating of high-k and metal gate of n/pMOS in different regions of the ...The key technologies for the dual high-k and dual metal gate, such as the electrical optimization of metal insert poly-Si stack structure, the separating of high-k and metal gate of n/pMOS in different regions of the wafer, and the synchronous etching of n/pMOS gate stack, are successfully developed. First, reasonable flat-band voltage and equivalent oxide thickness of pMOS MIPS structure are obtained by further optimizing the HfSiAlON dielectric through incorporating more Al-O dipole at interface between HfSiAlON and bottom SiOx. Then, the separating of high-k and metal gate for n/pMOS is achieved by SC1(NH4OH:H2O2:H2O = 1 : 1 : 5) and DHF-based solution for the selective removing of n MOS TaN and Hf Si ON and by BCl3-based plasma and DHF-based solution for the selective removing of pMOS TaN/Mo and HfSiAlON.After that, the synchronous etching of n/pMOS gate stack is developed by utilizing optimized BCl3/SF6/O2/Ar plasma to obtain a vertical profile for TaN and TaN/Mo and by utilizing BCl3/Ar plasma combined with DHF-based solution to achieve high selectivity to Si substrate. Finally, good electrical characteristics of CMOS devices, obtained by utilizing these new developed technologies, further confirm that they are practicable technologies for DHDMG integration.展开更多
High dielectric constant (high-k) materials are vital to the nanoelectronic devices. The paper reviews research development of high-k materials, describes a variety of manufacture technologies and discusses the applic...High dielectric constant (high-k) materials are vital to the nanoelectronic devices. The paper reviews research development of high-k materials, describes a variety of manufacture technologies and discusses the application of the gate stack systems to non-classical device structures.展开更多
An analytical direct tunneling gate current model for cylindrical surrounding gate(CSG) MOSFETs with high-k gate stacks is developed. It is found that the direct tunneling gate current is a strong function of the g...An analytical direct tunneling gate current model for cylindrical surrounding gate(CSG) MOSFETs with high-k gate stacks is developed. It is found that the direct tunneling gate current is a strong function of the gate's oxide thickness, but that it is less affected by the change in channel radius. It is also revealed that when the thickness of the equivalent oxide is constant, the thinner the first layer, the smaller the direct tunneling gate current.Moreover, it can be seen that the dielectric with a higher dielectric constant shows a lower tunneling current than expected. The accuracy of the analytical model is verified by the good agreement of its results with those obtained by the three-dimensional numerical device simulator ISE.展开更多
The time zero dielectric breakdown characteristics of MOSCAP with ultra-thin EOT high-k metal gate stacks are studied. The TZDB results show an abnormal area dependence due to the series resistance effect. The series ...The time zero dielectric breakdown characteristics of MOSCAP with ultra-thin EOT high-k metal gate stacks are studied. The TZDB results show an abnormal area dependence due to the series resistance effect. The series resistance components extracted from the Fowler-Nordheim tunneling relation are attributed to the spreading resistance due to the asymmetry electrodes. Based on a series model to eliminate the series resistance effect, an area acceleration dependence is obtained by correcting the TZDB results. The area dependence follows Poisson area scaling rules, which indicates that the mechanism of TZDB is the same as TDDB and could be considered as a trap generation process.展开更多
A semi-empirical analytic model for the threshold voltage instability of a MOSFET is derived from Shockley-Read-Hall (SRH) statistics to account for the transient charging effects in a MOSFET high-k gate stack. Star...A semi-empirical analytic model for the threshold voltage instability of a MOSFET is derived from Shockley-Read-Hall (SRH) statistics to account for the transient charging effects in a MOSFET high-k gate stack. Starting from the single energy level and single trap assumption, an analytical expression for the filled trap density in terms of dynamic time is derived from SRH statistics. The semi-empirical analytic model for the threshold voltage instability is developed based on MOSFET device physics between the threshold voltage and the induced trap density. The obtained model is also verified by extensive experimental data of trapping and de-trapping stress from different high-k gate configurations.展开更多
Although metal gate/high-k stacks are commonly used in metal-oxide-semiconductor field-effect-transistors (MOSFETs) in the 45 nm technology node and beyond,there are still many challenges to be solved.Among the variou...Although metal gate/high-k stacks are commonly used in metal-oxide-semiconductor field-effect-transistors (MOSFETs) in the 45 nm technology node and beyond,there are still many challenges to be solved.Among the various technologies to tackle these problems,interface dipole engineering (IDE) is an effective method to improve the performance,particularly,modulating the effective work function (EWF) of metal gates.Because of the different electronegativity of the various atoms in the interfacial layer,a dipole layer with an electric filed can be formed altering the band alignment in the MOS stack.This paper reviews the interface dipole formation induced by different elements,recent progresses in metal gate/high-k MOS stacks with IDE on EWF modulation,and mechanism of IDE.展开更多
基金support from Natural Science Foundation of Jiangsu Province (ProjectNo. BK2007130)National Natural Science Foundation of China (Grant Nos. 10874065, 60576023 and 60636010)+3 种基金Ministry of Science and Technology of China (Grant No.2009CB929503)Ministry of Science and Technology of China (Grant Nos. 2009CB929503 and2009ZX02101-4)the project sponsored by the Scientific Research Foundation for the Returned Overseas Chinese Scholars, State Education MinistryNational Found for Fostering Talents of Basic Science (NFFTBS) (ProjectNo. J0630316)
文摘The decreasing feature sizes in complementary metal-oxide semiconductor (CMOS) transistor technology will require the replacement of SiO2 with gate dielectrics that have a high dielectric constant (high-k) because as the SiO2 gate thickness is reduced below 1.4 nm, electron tunnelling effects and high leakage currents occur in SiO2, which present serious obstacles to future device reliability. In recent years significant progress has been made on the screening and selection of high-k gate dielectrics, understanding their physical properties, and their integration into CMOS technology. Now the family of hafnium oxide-based materials has emerged as the leading candidate for high-k gate dielectrics due to their excellent physical properties. It is also realized that the high-k oxides must be implemented in conjunction with metal gate electrodes to get sufficient potential for CMOS continue scaling. In the advanced nanoscale Si-based CMOS devices, the composition and thickness of interfacial layers in the gate stacks determine the critical performance of devices. Therefore, detailed atomic- scale understandings of the microstructures and interfacial structures built in the advanced CMOS gate stacks, are highly required. In this paper, several high-resolution electron, ion, and photon-based techniques currently used to characterize the high-k gate dielectrics and interfaces at atomic-scale, are reviewed. Particularly, we critically review the research progress on the characterization of interface behavior and structural evolution in the high-k gate dielectrics by high-resolution transmission electron microscopy (HRTEM) and the related techniques based on scanning transmission electron microscopy (STEM), including high-angle annular dark- field (HAADF) imaging (also known as Z-contrast imaging), electron energy-loss spectroscopy (EELS), and energy dispersive X-ray spectroscopy (EDS), due to that HRTEM and STEM have become essential metrology tools for characterizing the dielectric gate stacks in the present and future generations of CMOS devices. In Section 1 of this review, the working principles of each technique are briefly introduced and their key features are outlined. In Section 2, microstructural characterizations of high-k gate dielectrics at atomic-scale by electron microscopy are critically reviewed by citing some recent results reported on high-k gate dielectrics. In Section 3, metal gate electrodes and the interfacial structures between high-k dielectrics and metal gates are discussed. The electron beam damage effects in high-k gate stacks are also evaluated, and their origins and prevention are described in Section 4. Finally, we end this review with personal perspectives towards the future challenges of atomic-scale material characterization in advanced CMOS gate stacks.
基金supported by the National Natural Science Foundation of China(Grant Nos.61076101 and 61204092)
文摘Based on the elastic trap-assisted tunneling mechanism in high-κgate stacks,a quantum percolation tunneling current 1/fγ noise model is proposed by incorporating quantum tunneling theory into the quantum percolation model.We conclude that the noise amplitude of the PSD(Power Spectral Density)for three stages,namely the fresh device,one-layer BD(breakdown),and two-layer BD,increases from 10-22→10-14→10-8 A2/Hz.Meanwhile,the noise exponent γ for the three stages,has the 1/f2type(γ→2),1/fγ type(γ→1~2),and 1/f type(γ→1),respectively.The simulation results are in good agreement with the experimental results.This model reasonably interprets the correlation between the bi-layer breakdown and the tunneling 1/fγ noise amplitude dependence and 1/fγ noise exponent dependence.These results provide a theoretical basis for the high-κ gate stacks bi-layer breakdown noise characterization methods.
基金Supported by the National Natural Science Foundation of China under Grant No 61306126
文摘Higher-s dielectric LaLuO3, deposited by molecular beam deposition, with TiN as gate stack is integrated into high-mobility Si/SiGe/SOI quantum-well p-type metal-oxide-semiconduetor field effect transistors. Threshold voltage shift and capacitance equivalent thickness shrink are observed, resulting from oxygen scavenging effect in LaLuO3 with ti-rich TiN after high temperature annealing. The mechanism of oxygen scavenging and its potential for resistive memory applications are analyzed and discussed.
基金Project supported by the National Natural Science Foundation of China (Grant Nos. 60976068 and 60936005)Cultivation Fund of the Key Scientific and Technical Innovation Project, Ministry of Education of China (Grant No. 708083),Cultivation Fund of the Key Scientific and Technical Innovation Project, Ministry of Education of China (Grant No. 200807010010)
文摘Based on the exact resultant solution of two-dimensional Poisson's equation, the novel two-dimensional models, which include surface potential, threshold voltage, subthreshold current and subthreshold swing, have been developed for gate stack symmetrical double-gate strained-Si MOSFETs. The models are verified by numerical simulation. Besides offering the physical insight into device physics, the model provides the basic designing guidance of further immunity of short channel effect of complementary metal-oxide-semiconductor (CMOS)-based device in a nanoscale regime.
基金General Research Institute for Nonferrous Metals Research Fund (82262)
文摘Gd2O3 thin films as high-κ gate dielectrics were deposited directly on Si(001) substrates by magnetron sputtering at a pressure of 1.3 Pa and different temperatures. X-ray diffraction results revealed that all the films grown from 450 to 570 ℃ were crystalline, and the Gd2O3 thin films consisted of a mixture of cubic and monoclinic phases. The growth temperature was a critical parameter for the phase constituents and their relative amount. Low temperature was favorable for the formation of cubic phase while higher temperature gave rise to more monoclinic phase. All the Gd2O3 thin films grown from different temperatures exhibited acceptable electrical properties, such as low leakage current density (JL) of 10-5 A/cm^2 at zero bias with capacitance equivalent SiO2 thickness in the range of 6-13 nm. Through the comparison between films grown at 450 and 570 ℃, the existence of monoclinic phase caused an increase in JL by nearly one order of magnitude and a reduction of effective dielectric constant from 17 to 9.
基金Project supported by the National Natural Science Foundation of China(Grant Nos.61176100 and 61274112)
文摘High-k gate dielectric Hf Ti ON Ga As metal-oxide–semiconductor(MOS) capacitors with La ON as interfacial passivation layer(IPL) and NH3- or N2-plasma surface pretreatment are fabricated, and their interfacial and electrical properties are investigated and compared with their counterparts that have neither La ON IPL nor surface treatment. It is found that good interface quality and excellent electrical properties can be achieved for a NH3-plasma pretreated Ga As MOS device with a stacked gate dielectric of Hf Ti ON/La ON. These improvements should be ascribed to the fact that the NH3-plasma can provide H atoms and NH radicals that can effectively remove defective Ga/As oxides. In addition, La ON IPL can further block oxygen atoms from being in-diffused, and Ga and As atoms from being out-diffused from the substrate to the high-k dielectric. This greatly suppresses the formation of Ga/As native oxides and gives rise to an excellent high-k/Ga As interface.
文摘In the present work, a two-dimensional(2D) analytical framework of triple material symmetrical gate stack(TMGS)DG-MOSFET is presented in order to subdue the short channel effects. A lightly doped channel along with triple material gate having different work functions and symmetrical gate stack structure, showcases substantial betterment in quashing short channel effects to a good extent. The device functioning amends in terms of improved exemption to threshold voltage roll-off, thereby suppressing the short channel effects. The encroachments of respective device arguments on the threshold voltage of the proposed structure are examined in detail. The significant outcomes are compared with the numerical simulation data obtained by using 2D ATLAS;device simulator to affirm and formalize the proposed device structure.
基金Project supported by the National Natural Science Foundation of China(Grant Nos.60936005 and 61076097)the Cultivation Fund of the Key Scientific and Technical Innovation Project of Ministry of Education of China(Grant No.708083)the Fundamental Research Funds for the Central Universities,China(Grant No.20110203110012)
文摘The fringing-induced barrier lowering(FIBL) effect of sub-100 nm MOSFETs with high-k gate dielectrics is investigated using a two-dimensional device simulator.An equivalent capacitance theory is proposed to explain the physics mechanism of the FIBL effect.The FIBL effect is enhanced and the short channel performance is degraded with increasing capacitance.Based on equivalent capacitance theory,the influences of channel length,junction depth,gate/lightly doped drain(LDD) overlap length,spacer material and spacer width on FIBL is thoroughly investigated.A stack gate dielectric is presented to suppress the FIBL effect.
基金Project supported by the National High Technology Research and Development Program of China(Grant No.2015AA010601)
文摘The key technologies for the dual high-k and dual metal gate, such as the electrical optimization of metal insert poly-Si stack structure, the separating of high-k and metal gate of n/pMOS in different regions of the wafer, and the synchronous etching of n/pMOS gate stack, are successfully developed. First, reasonable flat-band voltage and equivalent oxide thickness of pMOS MIPS structure are obtained by further optimizing the HfSiAlON dielectric through incorporating more Al-O dipole at interface between HfSiAlON and bottom SiOx. Then, the separating of high-k and metal gate for n/pMOS is achieved by SC1(NH4OH:H2O2:H2O = 1 : 1 : 5) and DHF-based solution for the selective removing of n MOS TaN and Hf Si ON and by BCl3-based plasma and DHF-based solution for the selective removing of pMOS TaN/Mo and HfSiAlON.After that, the synchronous etching of n/pMOS gate stack is developed by utilizing optimized BCl3/SF6/O2/Ar plasma to obtain a vertical profile for TaN and TaN/Mo and by utilizing BCl3/Ar plasma combined with DHF-based solution to achieve high selectivity to Si substrate. Finally, good electrical characteristics of CMOS devices, obtained by utilizing these new developed technologies, further confirm that they are practicable technologies for DHDMG integration.
文摘High dielectric constant (high-k) materials are vital to the nanoelectronic devices. The paper reviews research development of high-k materials, describes a variety of manufacture technologies and discusses the application of the gate stack systems to non-classical device structures.
基金Project supported by the National Natural Science Foundation of China(Nos.61076101,61204092)the Fundamental Research Fundsfor the Central Universities of China(No.K50511250001)
文摘An analytical direct tunneling gate current model for cylindrical surrounding gate(CSG) MOSFETs with high-k gate stacks is developed. It is found that the direct tunneling gate current is a strong function of the gate's oxide thickness, but that it is less affected by the change in channel radius. It is also revealed that when the thickness of the equivalent oxide is constant, the thinner the first layer, the smaller the direct tunneling gate current.Moreover, it can be seen that the dielectric with a higher dielectric constant shows a lower tunneling current than expected. The accuracy of the analytical model is verified by the good agreement of its results with those obtained by the three-dimensional numerical device simulator ISE.
基金Project supported by the National High Technology Research and Development Program(863 Program)of China(No.SS2015AA010601)the National Natural Science Foundation of China(Nos.61176091+1 种基金61306129)the Opening Project of the Key Laboratory of Microelectronics Devices&Integrated Technology,Institute of Microelectronics,Chinese Academy of Sciences
文摘The time zero dielectric breakdown characteristics of MOSCAP with ultra-thin EOT high-k metal gate stacks are studied. The TZDB results show an abnormal area dependence due to the series resistance effect. The series resistance components extracted from the Fowler-Nordheim tunneling relation are attributed to the spreading resistance due to the asymmetry electrodes. Based on a series model to eliminate the series resistance effect, an area acceleration dependence is obtained by correcting the TZDB results. The area dependence follows Poisson area scaling rules, which indicates that the mechanism of TZDB is the same as TDDB and could be considered as a trap generation process.
基金supported by the Special Funds for the State Key Development Program for Basic Research of Chinathe National Natural Science Foundation of China (No.60876027)
文摘A semi-empirical analytic model for the threshold voltage instability of a MOSFET is derived from Shockley-Read-Hall (SRH) statistics to account for the transient charging effects in a MOSFET high-k gate stack. Starting from the single energy level and single trap assumption, an analytical expression for the filled trap density in terms of dynamic time is derived from SRH statistics. The semi-empirical analytic model for the threshold voltage instability is developed based on MOSFET device physics between the threshold voltage and the induced trap density. The obtained model is also verified by extensive experimental data of trapping and de-trapping stress from different high-k gate configurations.
基金supported by the National Natural Science Foundation of China(51172009,51172013 and 11074020)Program for New Century Excellent Talents in University(NCET-08-0029)+1 种基金Hong Kong Research Grants Council(RGC)General Research Funds(GRF)(CityU112510)City University of Hong Kong Strategic Research Grant(SRG)(7008009)
文摘Although metal gate/high-k stacks are commonly used in metal-oxide-semiconductor field-effect-transistors (MOSFETs) in the 45 nm technology node and beyond,there are still many challenges to be solved.Among the various technologies to tackle these problems,interface dipole engineering (IDE) is an effective method to improve the performance,particularly,modulating the effective work function (EWF) of metal gates.Because of the different electronegativity of the various atoms in the interfacial layer,a dipole layer with an electric filed can be formed altering the band alignment in the MOS stack.This paper reviews the interface dipole formation induced by different elements,recent progresses in metal gate/high-k MOS stacks with IDE on EWF modulation,and mechanism of IDE.