Challenges in Atomic-Scale Characterization of High-k Dielectrics and Metal Gate Electrodes for Advanced CMOS Gate Stacks

The decreasing feature sizes in complementary metal-oxide semiconductor （CMOS） transistor technology will require the replacement of SiO2 with gate dielectrics that have a high dielectric constant （high-k） because as the SiO2 gate thickness is reduced below 1.4 nm, electron tunnelling effects and high leakage currents occur in SiO2, which present serious obstacles to future device reliability. In recent years significant progress has been made on the screening and selection of high-k gate dielectrics, understanding their physical properties, and their integration into CMOS technology. Now the family of hafnium oxide-based materials has emerged as the leading candidate for high-k gate dielectrics due to their excellent physical properties. It is also realized that the high-k oxides must be implemented in conjunction with metal gate electrodes to get sufficient potential for CMOS continue scaling. In the advanced nanoscale Si-based CMOS devices, the composition and thickness of interfacial layers in the gate stacks determine the critical performance of devices. Therefore, detailed atomic- scale understandings of the microstructures and interfacial structures built in the advanced CMOS gate stacks, are highly required. In this paper, several high-resolution electron, ion, and photon-based techniques currently used to characterize the high-k gate dielectrics and interfaces at atomic-scale, are reviewed. Particularly, we critically review the research progress on the characterization of interface behavior and structural evolution in the high-k gate dielectrics by high-resolution transmission electron microscopy （HRTEM） and the related techniques based on scanning transmission electron microscopy （STEM）, including high-angle annular dark- field （HAADF） imaging （also known as Z-contrast imaging）, electron energy-loss spectroscopy （EELS）, and energy dispersive X-ray spectroscopy （EDS）, due to that HRTEM and STEM have become essential metrology tools for characterizing the dielectric gate stacks in the present and future generations of CMOS devices. In Section 1 of this review, the working principles of each technique are briefly introduced and their key features are outlined. In Section 2, microstructural characterizations of high-k gate dielectrics at atomic-scale by electron microscopy are critically reviewed by citing some recent results reported on high-k gate dielectrics. In Section 3, metal gate electrodes and the interfacial structures between high-k dielectrics and metal gates are discussed. The electron beam damage effects in high-k gate stacks are also evaluated, and their origins and prevention are described in Section 4. Finally, we end this review with personal perspectives towards the future challenges of atomic-scale material characterization in advanced CMOS gate stacks.

Quantum percolation tunneling current 1/f^γ noise model for high-κ gate stacks Bi-layer breakdown

Based on the elastic trap-assisted tunneling mechanism in high-κgate stacks,a quantum percolation tunneling current 1/fγ noise model is proposed by incorporating quantum tunneling theory into the quantum percolation model.We conclude that the noise amplitude of the PSD(Power Spectral Density)for three stages,namely the fresh device,one-layer BD(breakdown),and two-layer BD,increases from 10-22→10-14→10-8 A2/Hz.Meanwhile,the noise exponent γ for the three stages,has the 1/f2type(γ→2),1/fγ type(γ→1~2),and 1/f type(γ→1),respectively.The simulation results are in good agreement with the experimental results.This model reasonably interprets the correlation between the bi-layer breakdown and the tunneling 1/fγ noise amplitude dependence and 1/fγ noise exponent dependence.These results provide a theoretical basis for the high-κ gate stacks bi-layer breakdown noise characterization methods.

Oxygen Scavenging Effect of LaLuO_3/TiN Gate Stack in High-Mobility Si/SiGe/SOI Quantum-Well Transistors

Higher-s dielectric LaLuO3, deposited by molecular beam deposition, with TiN as gate stack is integrated into high-mobility Si/SiGe/SOI quantum-well p-type metal-oxide-semiconduetor field effect transistors. Threshold voltage shift and capacitance equivalent thickness shrink are observed, resulting from oxygen scavenging effect in LaLuO3 with ti-rich TiN after high temperature annealing. The mechanism of oxygen scavenging and its potential for resistive memory applications are analyzed and discussed.

融合Stacking框架的BiGRU-LGB云负载预测模型

随着云计算技术的飞速发展,越来越多的用户将应用部署在云平台上.。平台内集群资源的调度可以提高云平台数据中心的实际利用率,而高效的云平台负载预测是解决集群资源调度问题的关键技术,因此本文建立了一种融合Stacking框架、多层BiGRU网络和LightGBM算法的云负载预测模型。该模型的结构主要包括两种学习器:首先是初级学习器,使用时间编码层处理原始负载序列并利用BiGRU网络参数少、信息学习完整的特点减少模型训练时间和隐藏层数,学习负载序列中的时间维度信息;使用经过特征工程处理的原始负载序列来高效训练LightGBM算法,学习负载序列中的特征维度信息。然后是次级学习器,利用GRU网络整合时间和特征维度的负载信息,完成整个负载预测模型的训练。通过两层学习器的共同学习提高整体负载预测模型的预测精度。在华为云集群数据集上进行实验,结果表明,与传统的单一预测模型BiGRU、LightGBM等以及现有的组合预测模型GRU-LSTM相比,融合Stacking的BiGRU-LGB模型的预测精度提升约13%,训练时间开销得到一定程度的降低。

Study on two-dimensional analytical models for symmetrical gate stack dual gate strained silicon MOSFETs

Based on the exact resultant solution of two-dimensional Poisson＇s equation, the novel two-dimensional models, which include surface potential, threshold voltage, subthreshold current and subthreshold swing, have been developed for gate stack symmetrical double-gate strained-Si MOSFETs. The models are verified by numerical simulation. Besides offering the physical insight into device physics, the model provides the basic designing guidance of further immunity of short channel effect of complementary metal-oxide-semiconductor （CMOS）-based device in a nanoscale regime.

Phase control of magnetron sputtering deposited Gd_2O_3 thin films as high-κ gate dielectrics

Gd2O3 thin films as high-κ gate dielectrics were deposited directly on Si（001） substrates by magnetron sputtering at a pressure of 1.3 Pa and different temperatures. X-ray diffraction results revealed that all the films grown from 450 to 570 ℃ were crystalline, and the Gd2O3 thin films consisted of a mixture of cubic and monoclinic phases. The growth temperature was a critical parameter for the phase constituents and their relative amount. Low temperature was favorable for the formation of cubic phase while higher temperature gave rise to more monoclinic phase. All the Gd2O3 thin films grown from different temperatures exhibited acceptable electrical properties, such as low leakage current density （JL） of 10-5 A/cm^2 at zero bias with capacitance equivalent SiO2 thickness in the range of 6-13 nm. Through the comparison between films grown at 450 and 570 ℃, the existence of monoclinic phase caused an increase in JL by nearly one order of magnitude and a reduction of effective dielectric constant from 17 to 9.

High-k gate dielectric GaAs MOS device with LaON as interlayer and NH_3-plasma surface pretreatment

High-k gate dielectric Hf Ti ON Ga As metal-oxide–semiconductor（MOS） capacitors with La ON as interfacial passivation layer（IPL） and NH3- or N2-plasma surface pretreatment are fabricated, and their interfacial and electrical properties are investigated and compared with their counterparts that have neither La ON IPL nor surface treatment. It is found that good interface quality and excellent electrical properties can be achieved for a NH3-plasma pretreated Ga As MOS device with a stacked gate dielectric of Hf Ti ON/La ON. These improvements should be ascribed to the fact that the NH3-plasma can provide H atoms and NH radicals that can effectively remove defective Ga/As oxides. In addition, La ON IPL can further block oxygen atoms from being in-diffused, and Ga and As atoms from being out-diffused from the substrate to the high-k dielectric. This greatly suppresses the formation of Ga/As native oxides and gives rise to an excellent high-k/Ga As interface.

A two-dimensional analytical modeling for channel potential and threshold voltage of short channel triple material symmetrical gate Stack(TMGS) DG-MOSFET

In the present work, a two-dimensional（2D） analytical framework of triple material symmetrical gate stack（TMGS）DG-MOSFET is presented in order to subdue the short channel effects. A lightly doped channel along with triple material gate having different work functions and symmetrical gate stack structure, showcases substantial betterment in quashing short channel effects to a good extent. The device functioning amends in terms of improved exemption to threshold voltage roll-off, thereby suppressing the short channel effects. The encroachments of respective device arguments on the threshold voltage of the proposed structure are examined in detail. The significant outcomes are compared with the numerical simulation data obtained by using 2D ATLAS;device simulator to affirm and formalize the proposed device structure.

The influence and explanation of fringing-induced barrier lowering on sub-100 nm MOSFETs with high-k gate dielectrics

The fringing-induced barrier lowering（FIBL） effect of sub-100 nm MOSFETs with high-k gate dielectrics is investigated using a two-dimensional device simulator.An equivalent capacitance theory is proposed to explain the physics mechanism of the FIBL effect.The FIBL effect is enhanced and the short channel performance is degraded with increasing capacitance.Based on equivalent capacitance theory,the influences of channel length,junction depth,gate/lightly doped drain（LDD） overlap length,spacer material and spacer width on FIBL is thoroughly investigated.A stack gate dielectric is presented to suppress the FIBL effect.

Key technologies for dual high-k and dual metal gate integration

The key technologies for the dual high-k and dual metal gate, such as the electrical optimization of metal insert poly-Si stack structure, the separating of high-k and metal gate of n/pMOS in different regions of the wafer, and the synchronous etching of n/pMOS gate stack, are successfully developed. First, reasonable flat-band voltage and equivalent oxide thickness of pMOS MIPS structure are obtained by further optimizing the HfSiAlON dielectric through incorporating more Al-O dipole at interface between HfSiAlON and bottom SiOx. Then, the separating of high-k and metal gate for n/pMOS is achieved by SC1（NH4OH：H2O2：H2O = 1 ： 1 ： 5） and DHF-based solution for the selective removing of n MOS TaN and Hf Si ON and by BCl3-based plasma and DHF-based solution for the selective removing of pMOS TaN/Mo and HfSiAlON.After that, the synchronous etching of n/pMOS gate stack is developed by utilizing optimized BCl3/SF6/O2/Ar plasma to obtain a vertical profile for TaN and TaN/Mo and by utilizing BCl3/Ar plasma combined with DHF-based solution to achieve high selectivity to Si substrate. Finally, good electrical characteristics of CMOS devices, obtained by utilizing these new developed technologies, further confirm that they are practicable technologies for DHDMG integration.

High dielectric constant materials and their application to IC gate stack systems

High dielectric constant (high-k) materials are vital to the nanoelectronic devices. The paper reviews research development of high-k materials, describes a variety of manufacture technologies and discusses the application of the gate stack systems to non-classical device structures.

基于堆叠稀疏去噪自编码器的混合入侵检测方法

针对高维数据场景下传统入侵检测方法特征提取困难、检测准确率低等问题,提出一种集成多种深度学习模型的混合入侵检测方法.该方法由特征降维算法和混合检测模型2部分组成.首先,利用堆叠稀疏去噪自编码器对原始数据进行特征降维,从而剔除可能存在的噪声干扰和冗余信息.然后,采用一维卷积神经网络和双向门控循环单元学习数据中的空间维度特征和时序维度特征,将融合后的空时特征通过注意力分配不同的权重系数,从而使有用的信息得到更好表达,再经由全连接层训练后进行分类.为检验方案的可行性,在UNSW-NB15数据集上进行验证.结果表明,该模型与其他同类型入侵检测算法相比,拥有更优秀的检测性能,其准确率达到99.57%,误报率仅为0.68%.

基于Stacking多GRU模型的风电场短期功率预测

为提高风电场短期功率预测的准确度,在深度学习的基础上提出利用Stacking算法集成融合多个GRU(Gated Recurrent Unit)模型的风电场短期功率预测的方法。该方法首先搭建3个多层GRU神经网络模型建立第1级模型,深度提取高维的时序特征关系,通过第1级模型的预测结果构建训练集,然后利用新生成的训练集训练第2级GRU模型,第2级的GRU模型采用单层结构,能发现并且纠正第1级模型中的预测误差,提升整体的预测结果。最终得到两级模型嵌入的Stacking融合模型。以宁夏太阳山风电场历史数据为例对该模型的准确性进行验证。实验结果表明,通过Stacking算法融合的GRU模型相比其他算法预测平均绝对百分比误差提高了0.63,总体预测效果较为理想,预测准确度提升明显。

基于MRSDAE-SOM结合HGRU的滚动轴承RUL预测

基于传统方法预测轴承剩余使用寿命(Residual Useful Life,RUL),步骤繁多,成本昂贵,且模型不具泛化性。现有的基于深度学习(Deep Learning,DL)的预测方法,由于数据量过大,经常导致模型出现过拟合现象,从而使模型精度不高。为了克服以上缺点,提出一种基于MRSDAE-SOM结合HGRU的滚动轴承RUL预测方法。首先,使用无监督式网络流形正则化堆栈去噪自编码器(Manifold Regularization Stack Denoising Auto Encoder,MRSDAE)结合自组织映射(Self-Or-ganizing Mapping,SOM)构建轴承健康因子(Health Indicator,HI)。然后,通过分层门控循环单元(Hierarchical Gated Re-current Unit,HGRU)网络建立预测模型,HGRU网络通过加入多尺度层和密集层,使其具有捕获时序特征且集成不同时间尺度注意力信息的能力。最后,通过实验验证表明,相比于其他基于数据驱动的方法,所提方法构建健康因子使用无监督方式,高效快捷且便于应用;预测模型泛化能力好,并有效防止了过拟合现象,实现了更高的预测精度。

ARM+FPGA双核计算的配电自动化终端设计

为了提高配电自动化终端数据信息自动化分析能力,设计了基于ARM+现场可编程门阵列(FPGA)双核计算的配电自动化终端。为了提高模块计算能力,在模块中构建了堆叠式自动编码器-神经网络(SAE-NN)深度学习算法模型。在常规堆叠式自动编码器(SAE)深度学习模型基础上融合神经网络(NN)模型,应用过程中改善传统NN对分层节点数目的限制。试验结果表明,所设计终端随着系统运行能达到95%以上的精度,而现有SAE模型仅达到85%左右的精度。通过与文献[1]和文献[2]方法的对比可知,所设计终端有较高的调度能力。该设计显著提高了配电网数据信息的分析精度,大幅提升了电网应用对数据信息处理的准确度和效率。

Analytical modeling of the direct tunneling current through high-k gate stacks for long-channel cylindrical surrounding-gate MOSFETs

An analytical direct tunneling gate current model for cylindrical surrounding gate（CSG） MOSFETs with high-k gate stacks is developed. It is found that the direct tunneling gate current is a strong function of the gate＇s oxide thickness, but that it is less affected by the change in channel radius. It is also revealed that when the thickness of the equivalent oxide is constant, the thinner the first layer, the smaller the direct tunneling gate current.Moreover, it can be seen that the dielectric with a higher dielectric constant shows a lower tunneling current than expected. The accuracy of the analytical model is verified by the good agreement of its results with those obtained by the three-dimensional numerical device simulator ISE.

超薄Si_3N_4/SiO_2(N/O)stack栅介质及器件

成功制备了EOT(equivalentoxidethickness)为 2 1nm的Si3 N4/SiO2 (N/O)stack栅介质 ,并对其性质进行了研究 .结果表明 ,同样EOT的Si3 N4/SiO2 stack栅介质和纯SiO2 栅介质比较 ,前者在栅隧穿漏电流、抗SILC性能、栅介质寿命等方面都远优于后者 .在此基础上 ,采用Si3 N4/SiO2 stack栅介质制备出性能优良的栅长为 0 12 μm的CMOS器件 ,器件很好地抑制了短沟道效应 .在Vds=Vgs=± 1 5V下 ,nMOSFET和pMOSFET对应的饱和电流Ion分别为5 84 3μA/ μm和 - 2 81 3μA/ μm ,对应Ioff分别是 8 3nA/ μm和 - 1 3nA/ μm .

Series resistance effect on time zero dielectrics breakdown characteristics of MOSCAP with ultra-thin EOT high-k/metal gate stacks

The time zero dielectric breakdown characteristics of MOSCAP with ultra-thin EOT high-k metal gate stacks are studied. The TZDB results show an abnormal area dependence due to the series resistance effect. The series resistance components extracted from the Fowler-Nordheim tunneling relation are attributed to the spreading resistance due to the asymmetry electrodes. Based on a series model to eliminate the series resistance effect, an area acceleration dependence is obtained by correcting the TZDB results. The area dependence follows Poisson area scaling rules, which indicates that the mechanism of TZDB is the same as TDDB and could be considered as a trap generation process.

A semi-empirical analytic model for threshold voltage instability in MOSFETs with high-k gate stacks

A semi-empirical analytic model for the threshold voltage instability of a MOSFET is derived from Shockley-Read-Hall （SRH） statistics to account for the transient charging effects in a MOSFET high-k gate stack. Starting from the single energy level and single trap assumption, an analytical expression for the filled trap density in terms of dynamic time is derived from SRH statistics. The semi-empirical analytic model for the threshold voltage instability is developed based on MOSFET device physics between the threshold voltage and the induced trap density. The obtained model is also verified by extensive experimental data of trapping and de-trapping stress from different high-k gate configurations.

Interface dipole engineering in metal gate/high-k stacks

Although metal gate/high-k stacks are commonly used in metal-oxide-semiconductor field-effect-transistors (MOSFETs) in the 45 nm technology node and beyond,there are still many challenges to be solved.Among the various technologies to tackle these problems,interface dipole engineering (IDE) is an effective method to improve the performance,particularly,modulating the effective work function (EWF) of metal gates.Because of the different electronegativity of the various atoms in the interfacial layer,a dipole layer with an electric filed can be formed altering the band alignment in the MOS stack.This paper reviews the interface dipole formation induced by different elements,recent progresses in metal gate/high-k MOS stacks with IDE on EWF modulation,and mechanism of IDE.