基于FPGA的异步FIFO缓存数据溢出控制系统

为获取更高效、稳定的缓存数据控制方法,设计基于现场可编程门阵列(field programmable gate array,FPGA)的异步FIFO缓存数据溢出控制系统。设计存储控制方案,得到基于FPGA的系统硬件;建立缓存数据存储溢出模型,得到数据节点剩余能量的最小值最大化求解,在函数模型下判断存储数据是否溢出;设计数据溢出控制算法,得到缓存数据溢出控制系统的软件。分别对数据溢出的监测性能与控制性能进行测试。实验结果表明:使用该方法剩余的能耗较高,可见该方法对于缓存数据的监测与控制性能均较好。

基于Chisel语言的异步FIFO设计及验证

采用敏捷硬件开发语言Chisel,对数字系统设计中经常使用的异步先进先出(FIFO)进行设计,使用Chisel语言特性提高了设计效率和质量。使用ChiselTest框架对所设计的异步FIFO进行基本功能仿真验证,使用通用验证方法学(UVM)进行更加完备的功能仿真验证,再使用QuartusⅡ软件进行逻辑综合。对比使用Chisel语言与使用传统硬件描述语言(HDL)设计的异步FIFO综合结果,结果表明,使用传统HDL语言设计的异步FIFO消耗了50个组合逻辑单元,而使用Chisel语言设计的异步FIFO,综合后仅消耗了39个组合逻辑单元。

基于STM32与异步FIFO的乒乓模式高速数据采集系统设计

针对电力行业光纤光栅传感器数据采集速率不足、功耗高等问题,设计了一种基于STM32与异步FIFO的高速数据采集系统。该系统以STM32为核心,通过采用TIADC结构来实现双通道交替采样,提高了系统采样率;各通道内利用两片异步FIFO实现乒乓缓存技术,完成了信号数据的高速存储与实时处理,并通过WIFI通信将数据传输到上位机。试验证明:该数据采样系统实现了低功耗的高速数据采集,存储深度为16 K,最高采样率可达200 Msample/s,可满足电力行业工程需求。

基于无锁FIFO队列的CAN总线数据采集系统

针对在CAN总线数据量大的应用场景下,CAN总线记录仪实车数据采集数据丢帧的问题及人工操作PC搭配CAN分析仪采集实车数据流程繁琐的问题,基于无锁FIFO队列算法设计了以STM32为核心控制器的CAN总线数据采集系统。系统分为软件和硬件两个部分:软件部分运用无锁FIFO队列算法,可根据CAN总线数据量的大小自适应调整队列缓冲区的大小,优化后可避免数据帧丢失;硬件部分以STM32为平台,搭载Micro SD卡模块,实现了无需人工操作使总线实车数据的采集脱离PC设备。经验证表明,该系统方案避免了CAN总线实车数据采集过程中数据丢帧问题,简化了实车数据采集流程,提高了实车数据采集效率。

Quantitative description of characteristics of high-capacity channels in unconsolidated sandstone reservoirs using in situ production data

Quantitative description of the high-capacity channels in unconsolidated sandstone reservoirs, into which water was injected to improve oil recovery, is a hot topic in the field of reservoir development. This paper presents a novel approach to describing quantitatively the characteristics of connected macropores in unconsolidated sandstone reservoirs using in situ production data. Based on physical simulation for formation mechanisms of high capacity channels and interwell tracer test data, a mathematical model was established to describe high-capacity channels by grey correlation theory, flow mechanism of fluid in porous media and reservoir engineering, and a program was developed to describe quantitatively the channel characteristics. The predicted results were consistent with field monitoring data （80%）, so this model could be economically and effectively used to identify high-capacity channels.

High-capacity three-party quantum secret sharing with superdense coding

This paper presents a scheme for high-capacity three-party quantum secret sharing with quantum superdense coding, following some ideas in the work by Liuet al （2002 Phys. Rev. A 65 022304） and the quantum secret sharing scheme by Deng et al （2008 Phys. Lett. A 372 1957）. Instead of using two sets of nonorthogonal states, the boss Alice needs only to prepare a sequence of Einstei^Podolsky-l^osen pairs in d-dimension. The two agents Bob and Charlie encode their information with dense coding unitary operations, and security is checked by inserting decoy photons. The scheme has a high capacity and intrinsic efficiency as each pair can carry 21bd bits of information, and almost all the pairs can be used for carrying useful information.

Stress release in high-capacity flexible lithium-ion batteries through nested wrinkle texturing of graphene

Flexible lithium-ion batteries(LIBs)are critical for the development of next-generation smart electronics.Conversion reaction-based electrodes have been considered promising to construct high energy-density flexible LIBs,which satisfy the ever-increasing demand for practical use.However,these electrodes suffer from inferior lithium-storage performance and structural instability during deformation and long-term lithiation/delithiation.These are caused by the sluggish reaction kinetics of active-materials and the superposition of responsive strains originating from the large lithiation-induced stress and applied stress.Here,we propose a stress-release strategy through elastic responses of nested wrinkle texturing of graphene,to achieve high deformability while maintaining structural integrity upon prolonged cycles within high-capacity electrodes.The wrinkles endow the electrode with a robust and flexible network for effective stress release.The resulting electrode shows large reversible stretchability,along with excellent electrochemical performance including high specific capacity,high-rate capability and long-term cycling stability.This strategy offers a new way to obtain high-performance flexible electrodes and can be extended to other energy-storage devices.

Atomic Layer Deposition of High-Capacity Anodes for Next-Generation Lithium-Ion Batteries and Beyond

Electrification has great impacts on our modern society.To electrify future transportation,state-of-the-art lithium-ion batteries(LIBs)are still not sufficient in multiple aspects including cost,energy density,lifespan,and safety.To this end,next-generation high-energy LIBs and beyond are highly regarded.In this regard,high-capacity anodes are undergoing intensive investigation,such as silicon,SnO_(2),and lithium metal.However,such anode materials are commonly experiencing large volume changes and related issues,which are reflected on mechanical degradation,capacity fading,low efficiency,and unsatisfactory lifetime.To address these challenges,many technical strategies have been investigated.In the past decade,atomic layer deposition(ALD)has emerged as a new promising technique enabling atomic-scale surface modification and nanoscale design of high-capacity anodes for high performance.In this review,recent ALD studies on developing high-capacity anodes for LIBs and beyond are thoroughly summarized.In addition,ALD strategies and their effectiveness in pursing high-energy LIBs and beyond are discussed.Particularly,we highlighted the latest advances of ALD for addressing the notorious issues associated with Li metal anodes.It is expected that this work will promote the applications of ALD in new battery systems.

High-Capacity Quantum Secure Communication with Authentication Using Einstein-Podolsky-Rosen Pairs

A new protocol for quantum secure communication with authentication is proposed. The proposed protocol has a higher capacity as each EPR pair can carry four classical bits by the XOR operation and an auxiliary photon. Tile security and efficiency are analyzed in detail and the major advantage of this protocol is that it is more efficient without losing security.

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基于磁悬浮织针阵列异步FIFO模块设计

针对磁悬浮织针阵列系统数据高速、实时传输的需求,结合磁悬浮织针阵列模型定义织针驱动数据格式,并依据循环队列原理在FPGA设计软件中设计异步FIFO缓存模块。利用其独特的环形结构特性,帮助数据传输系统实现驱动数据的高速传输。为避免数据溢出造成数据传输错误情况的出现,在FIFO模块中加入空、满判断功能。仿真结果表明,该FIFO模块能够实现多路磁悬浮织针的驱动数据高速缓存,并及时反馈循环队列中数据存取情况,验证了该方案实现磁悬浮织针横机数据高速传输的有效性与可行性。

异步FIFO抗SEU设计

在高空高能粒子的影响下,航天或航空电子设计中广泛使用的异步FIFO容易产生单粒子翻转,从而导致功能紊乱甚至失效。因此在面向航天或航空的高安全电子设计中需采用容错设计来提高异步FIFO电路的抗辐射能力。但传统的三模冗余设计应用于异步FIFO时有一定的局限性,会出现由指针错误引起的某一通道的数据持续出错、跨时钟域导致的输出数据不同步等降低三模冗余防护能力的问题。针对该问题,文中提出适用于异步FIFO的新的电路结构及三模冗余方案。经仿真证明,采用新三模冗余方案构建的异步FIFO在辐射环境下能快速纠正指针错误,同步三路冗余数据,使其具有更高的单粒子防护效果。

基于FIFO的色选机分选系统设计

针对以处理器为核心的多通道色选机色选信号延时精度低、一致性差和连续信号丢失等缺点,设计了以现场可编程逻辑门阵列(Field-Programmable Gate Array,FPGA)为控制核心的色选机分选系统。该系统通过485总线与人机界面实现参数和系统状态的实时传递;利用FPGA程序并行执行的特点实现检测信号串并转换;把FPGA内部RAM配置成同步先入先出存储器(First Input First Output,FIFO),并利用FIFO数据先入先出的特点实现多路检测信号的精确无损延时,并行产生多路分选脉冲信号。仿真和实验结果表明,该设计满足多通道、高产量、高检出率、高精度的色选机对分选系统的要求,显著提高了色选机的检出水平和产量。

使用排队论模型对FIFO深度的研究

长期以来FIFO研究偏重于降低单元间传输延时,所建立的模型不能满足对其它参数研究的要求。特别是FIFO深度,一般依靠设计者经验给出,尚未有理论上的解决方案。当可重构技术应用日趋成熟,可重构系统芯片功能可由应用工程师最终确定时,FIFO深度选取问题更加突出。针对上述问题,本文提出了一种基于排队论的新型FIFO模型,使用该模型探讨了FIFO深度问题,阐述了FIFO深度的理论含义,并给出了FIFO深度理论计算公式。

基于FPGA的高速数据存储系统中FIFO控制的设计

介绍了一种高速CCD相机数据存储中的FIFO缓存控制的方法。利用FPGA对高速数据存储系统中的FIFO缓存器进行控制,在QuartusⅡ开发平台上进行设计仿真,结果表明数据流和IDE硬盘之间的存储速率得到匹配,数据实时存储到硬盘中,为后期的数据处理提供了原始数据,同时也为存储系统的设计提供了参考。

基于FIFO技术的数据采集系统研究

数据采集系统[1]是工业CT[1](Industrial Computed Tomography--ICT)的重要组成部分,保证数据采集系统工作的稳定、可靠和一致性,对于研制和改进其质量和提高工业CT整体性能有着重要的意义.在Windows操作系统下,程序查询的教据传输方式会因为其它程序的中断造成数据丢失,针对这一问题,对工业CT的数据采集系统进行了设计与研究[3].将程序查询方式改为中断方式,在计数逻辑电路的数据通道前端加上FIFO缓存,从而保证了数据采集和传输的可靠和稳定性.

片上网络FIFOs的内建自测试方法研究

片上网络是对微系统芯片的传统片上互连结构的统一和发展,一种新的集成电路设计技术只有在它的测试技术发展完善后才能被广泛使用。首先建立了片上网络路由器FIFOs的功能模型,在此基础上,提出了一种基于可测性设计技术并且具有线性计算复杂度O(n)的FIFOs测试算法,论述了一种新颖的复用片上网络、共享内建自测试(BIST)结构对片上网络路由器FIFOs并行测试的方法。实验数据分析表明这种测试方法具有较高的故障覆盖率、较小的测试时间和片上资源开销。

异步FIFO状态判断的研究与设计

研究了异步FIFO状态判断的问题,提出了一种能快速准确判断异步FIFO空、满和半满状态的方案,设计了状态判断的逻辑电路并给出了物理实现。

基于DDR2 SDRAM的高速大容量异步FIFO的设计与实现

为了解决高速实时系统中海量数据的缓存问题,提出了一种基于DDR2 SDRAM的高速大容量异步FIFO设计方案。首先介绍了DDR2 SDRAM控制器和片上FIFO的原理与实现方法,基于DDR2 SDRAM的高带宽和分时复用技术设计了FIFO控制器的工作机制,最后深入分析了FIFO控制器各部分的工作原理并对其进行了实验。经过测试,基于DDR2 SDRAM的FIFO实现了最高475MHz的总线速率,8～256位的总线位宽,2GB最大数据容量。该FIFO可以解决高速海量数据缓存的问题,在工程应用中有显著的参考价值。

基于FPGA视频和图像处理系统的FIFO缓存技术

通过研究视频图像处理和视频图像帧格式以及FIFO缓存技术,提出了基于FPGA的视频图像处理系统设计。该设计运用帧间差分法、同步FIFO缓存设计,有效避免了图像处理系统设计中亚稳态和异步信号处理等时序性难题,实现了视频图像序列的动态目标检测系统设计。ChipScope在线逻辑分析结果表明,所设计的系统具有实时的视频图像处理性能,与基于外接存储器缓存的系统设计相比较,稳定性更高,实时性更好,功耗更低。