Challenges in Atomic-Scale Characterization of High-k Dielectrics and Metal Gate Electrodes for Advanced CMOS Gate Stacks

The decreasing feature sizes in complementary metal-oxide semiconductor （CMOS） transistor technology will require the replacement of SiO2 with gate dielectrics that have a high dielectric constant （high-k） because as the SiO2 gate thickness is reduced below 1.4 nm, electron tunnelling effects and high leakage currents occur in SiO2, which present serious obstacles to future device reliability. In recent years significant progress has been made on the screening and selection of high-k gate dielectrics, understanding their physical properties, and their integration into CMOS technology. Now the family of hafnium oxide-based materials has emerged as the leading candidate for high-k gate dielectrics due to their excellent physical properties. It is also realized that the high-k oxides must be implemented in conjunction with metal gate electrodes to get sufficient potential for CMOS continue scaling. In the advanced nanoscale Si-based CMOS devices, the composition and thickness of interfacial layers in the gate stacks determine the critical performance of devices. Therefore, detailed atomic- scale understandings of the microstructures and interfacial structures built in the advanced CMOS gate stacks, are highly required. In this paper, several high-resolution electron, ion, and photon-based techniques currently used to characterize the high-k gate dielectrics and interfaces at atomic-scale, are reviewed. Particularly, we critically review the research progress on the characterization of interface behavior and structural evolution in the high-k gate dielectrics by high-resolution transmission electron microscopy （HRTEM） and the related techniques based on scanning transmission electron microscopy （STEM）, including high-angle annular dark- field （HAADF） imaging （also known as Z-contrast imaging）, electron energy-loss spectroscopy （EELS）, and energy dispersive X-ray spectroscopy （EDS）, due to that HRTEM and STEM have become essential metrology tools for characterizing the dielectric gate stacks in the present and future generations of CMOS devices. In Section 1 of this review, the working principles of each technique are briefly introduced and their key features are outlined. In Section 2, microstructural characterizations of high-k gate dielectrics at atomic-scale by electron microscopy are critically reviewed by citing some recent results reported on high-k gate dielectrics. In Section 3, metal gate electrodes and the interfacial structures between high-k dielectrics and metal gates are discussed. The electron beam damage effects in high-k gate stacks are also evaluated, and their origins and prevention are described in Section 4. Finally, we end this review with personal perspectives towards the future challenges of atomic-scale material characterization in advanced CMOS gate stacks.

Investigation of degradation and recovery characteristics of NBTI in 28-nm high-k metal gate process

Degradation induced by the negative bias temperature instability(NBTI)can be attributed to three mutually uncoupled physical mechanisms,i.e.,the generation of interface traps(ΔV_(IT)),hole trapping in pre-existing gate oxide defects(ΔV_(HT)),and the generation of gate oxide defects(ΔV_(OT)).In this work,the characteristic of NBTI for p-type MOSFET fabricated by using a 28-nm high-k metal gate(HKMG)process is thoroughly studied.The experimental results show that the degradation is enhanced at a larger stress bias and higher temperature.The effects of the three underlying subcomponents are evaluated by using the comprehensive models.It is found that the generation of interface traps dominates the NBTI degradation during long-time NBTI stress.Moreover,the NBTI parameters of the power-law time exponent and temperature activation energy as well as the gate oxide field acceleration are extracted.The dependence of operating lifetime on stress bias and temperature is also discussed.It is observed that NBTI lifetime significantly decreases as the stress increases.Furthermore,the decrease of charges related to interface traps and hole detrapping in pre-existing gate oxide defects are used to explain the recovery mechanism after stress.

Analysis of flatband voltage shift of metal/high-k/SiO_2/Si stack based on energy band alignment of entire gate stack

A theoretical model of flatband voltage （VFB） of metal/high-k/Si02/Si stack is proposed based on band alignment of entire gate stack, i.e., the VFB is obtained by simultaneously considering band alignments of metal/high-k, high-k/SiO2 and SiO2/Si interfaces, and their interactions. Then the VFB of TiN/HfO2/SiO2/Si stack is experimentally obtained and theoretically investigated by this model. The theoretical calculations are in good agreement with the experimental results. Furthermore, both positive VFB shift of TiN/HfO2/SiO2/Si stack and Fermi level pinning are successfully interpreted and attributed to the dielectric contact induced gap states at TiN/HfO2 and HfO2/SiO2 interfaces.

Flat-band voltage shift in metal-gate/high-k/Si stacks

In metal-gate/high-k stacks adopted by the 45 nm technology node, the fiat-band voltage （Vfb） shift remains one of the most critical challenges, particularly the flat-band voltage roll-off （Vfb roll-off） phenomenon in p-channel metal- oxide-semiconductor （pMOS） devices with an ultrathin oxide layer. In this paper, recent progress on the investigation of the Vfb shift and the origin of the Vfb roll-off in the metal-gate/high-k pMOS stacks are reviewed. Methods that can alleviate the Vfb shift phenomenon are summarized and the future research trend is described.

Study on influences of TiN capping layer on time-dependent dielectric breakdown characteristic of ultra-thin EOT high-k metal gate NMOSFET with kMC TDDB simulations

The thickness effect of the TiN capping layer on the time dependent dielectric breakdown（TDDB） characteristic of ultra-thin EOT high-k metal gate NMOSFET is investigated in this paper.Based on experimental results,it is found that the device with a thicker TiN layer has a more promising reliability characteristic than that with a thinner TiN layer.From the charge pumping measurement and secondary ion mass spectroscopy（SIMS） analysis,it is indicated that the sample with the thicker TiN layer introduces more Cl passivation at the IL/Si interface and exhibits a lower interface trap density.In addition,the influences of interface and bulk trap density ratio Nit/Not are studied by TDDB simulations through combining percolation theory and the kinetic Monte Carlo（kMC） method.The lifetime reduction and Weibull slope lowering are explained by interface trap effects for TiN capping layers with different thicknesses.

Temperature- and voltage-dependent trap generation model in high-k metal gate MOS device with percolation simulation

High-k metal gate stacks are being used to suppress the gate leakage due to tunneling for sub-45 nm technology nodes.The reliability of thin dielectric films becomes a limitation to device manufacturing,especially to the breakdown characteristic.In this work,a breakdown simulator based on a percolation model and the kinetic Monte Carlo method is set up,and the intrinsic relation between time to breakdown and trap generation rate R is studied by TDDB simulation.It is found that all degradation factors,such as trap generation rate time exponent m,Weibull slope β and percolation factor s,each could be expressed as a function of trap density time exponent α.Based on the percolation relation and power law lifetime projection,a temperature related trap generation model is proposed.The validity of this model is confirmed by comparing with experiment results.For other device and material conditions,the percolation relation provides a new way to study the relationship between trap generation and lifetime projection.

Key technologies for dual high-k and dual metal gate integration

The key technologies for the dual high-k and dual metal gate, such as the electrical optimization of metal insert poly-Si stack structure, the separating of high-k and metal gate of n/pMOS in different regions of the wafer, and the synchronous etching of n/pMOS gate stack, are successfully developed. First, reasonable flat-band voltage and equivalent oxide thickness of pMOS MIPS structure are obtained by further optimizing the HfSiAlON dielectric through incorporating more Al-O dipole at interface between HfSiAlON and bottom SiOx. Then, the separating of high-k and metal gate for n/pMOS is achieved by SC1（NH4OH：H2O2：H2O = 1 ： 1 ： 5） and DHF-based solution for the selective removing of n MOS TaN and Hf Si ON and by BCl3-based plasma and DHF-based solution for the selective removing of pMOS TaN/Mo and HfSiAlON.After that, the synchronous etching of n/pMOS gate stack is developed by utilizing optimized BCl3/SF6/O2/Ar plasma to obtain a vertical profile for TaN and TaN/Mo and by utilizing BCl3/Ar plasma combined with DHF-based solution to achieve high selectivity to Si substrate. Finally, good electrical characteristics of CMOS devices, obtained by utilizing these new developed technologies, further confirm that they are practicable technologies for DHDMG integration.

Influence of multi-deposition multi-annealing on time-dependent dielectric breakdown characteristics of PMOS with high-k/metal gate last process

A multi-deposition multi-annealing technique （MDMA） is introduced into the process of high-k/metal gate MOSFET for the gate last process to effectively reduce the gate leakage and improve the device＇s performance. In this paper, we systematically investigate the electrical parameters and the time-dependent dielectric breakdown （TDDB） characteristics of positive channel metal oxide semiconductor （PMOS） under different MDMA process conditions, including the depo- sition/annealing （D＆A） cycles, the D＆A time, and the total annealing time. The results show that the increases of the number of D＆A cycles （from 1 to 2） and D＆A time （from 15 s to 30 s） can contribute to the results that the gate leakage current decreases by about one order of magnitude and that the time to fail （TTF） at 63.2% increases by about several times. However, too many D＆A cycles （such as 4 cycles） make the equivalent oxide thickness （EOT） increase by about 1A and the TTF of PMOS worsen. Moreover, different D＆A times and numbers of D＆A cycles induce different breakdown mechanisms.

28nm HKMG技术中镍硅化物异常生长引发的失效

针对28nm高介电常数金属栅(HKMG)技术研发初期出现的镍硅化物异常导致的失效进行了深入探究。发现第二道镍硅化物激光退火工艺对产品良率有重要影响。对裸晶内失效位置进行透射电子显微镜(TEM)检测,结果表明失效区域均为PMOS器件的SiGe区域。这意味着在相同的热预算条件下,PMOS的工艺窗口相较于NMOS会更狭窄。结合激光退火工艺特性,在首次扫描过程中,受降温阶段的影响,晶圆特定区域会累积额外热量,使得该区域热预算异常升高,镍硅化物产生异常,导致产品良率损失;当激光退火温度降低40℃,镍硅化物缺陷问题得以成功解决,产品良率也得到明显提升。

Stress-induced leakage current characteristics of PMOS fabricated by a new multi-deposition multi-annealing technique with full gate last process

In the process of high-k films fabrication, a novel multi deposition multi annealing （MDMA） technique is introduced to replace simple post deposition annealing. The leakage current decreases with the increase of the post deposition annealing （PDA） times. The equivalent oxide thickness （EOT） decreases when the annealing time（s） change from 1 to 2. Furthermore, the characteristics of SILC （stress-induced leakage current） for an ultra-thin SiO2/HfO2 gate dielectric stack are studied systematically. The increase of the PDA time（s） from 1 to 2 can decrease the defect and defect generation rate in the HK layer. However, increasing the PDA times to 4 and 7 may introduce too much oxygen, therefore the type of oxygen vacancy changes.

Combining a multi deposition multi annealing technique with a scavenging(Ti) to improve the high-k/metal gate stack performance for a gate-last process

ALD HfO2 films fabricated by a novel multi deposition multi annealing （MDMA） technique are inves- tigated, we have included samples both with and without a Ti scavenging layer. As compared to the reference gate stack treated by conventional one-time deposition and annealing （D＆A）, devices receiving MDMA show a signif- icant reduction in leakage current. Meanwhile, EOT growth is effectively controlled by the Ti scavenging layer. This improvement strongly correlates with the cycle number of D＆A （while keeping the total annealing time and total dielectrics thickness the same）. Transmission electron microscope and energy-dispersive X-ray spectroscopy analysis suggests that oxygen incorporation into both the high-k film and the interfacial layer is likely to be re- sponsible for the improvement of the device. This novel MDMA is promising for the development of gate stack technology in a gate last integration scheme.

Series resistance effect on time zero dielectrics breakdown characteristics of MOSCAP with ultra-thin EOT high-k/metal gate stacks

The time zero dielectric breakdown characteristics of MOSCAP with ultra-thin EOT high-k metal gate stacks are studied. The TZDB results show an abnormal area dependence due to the series resistance effect. The series resistance components extracted from the Fowler-Nordheim tunneling relation are attributed to the spreading resistance due to the asymmetry electrodes. Based on a series model to eliminate the series resistance effect, an area acceleration dependence is obtained by correcting the TZDB results. The area dependence follows Poisson area scaling rules, which indicates that the mechanism of TZDB is the same as TDDB and could be considered as a trap generation process.

Characterization of positive bias temperature instability of NMOSFET with high-k/metal gate last process

Positive bias temperature instability（PBTI） characteristics and degradation mechanisms of NMOSFET with high-k/metal gate last process have been systematically investigated. The time evolution of threshold voltage shift during PBTI stress still follows a power law. However, the exponent n decreases from 0.26 to 0.16 linearly as the gate stress voltage increases from 0.6 to 1.2 V. There is no interface state generation during stress because of the negligible sub-threshold swing change. Moreover, the activation energy is 0.1 e V, which implies that electrons directly tunnel into high-k bulk and are trapped by pre-existing traps resulting into PBTI degradation. During recovery the threshold voltage shift is linear in lgt, and a mathematical model is proposed to express threshold voltage shift.

磨料粒径对铝栅CMP去除速率和粗糙度的影响

在铝栅化学机械平坦化(CMP)中磨料直接影响去除速率和表面粗糙度。采用不同粒径的磨料配置抛光液对铝栅进行CMP实验,对去除速率和表面形貌测试结果进行分析。结果表明,去除速率与参与抛光的磨料颗粒数目和单个颗粒去除速率有关,表面粗糙度与单个磨料颗粒机械作用和抛光后磨料颗粒表面吸附有关,并对抛光液稳定性进行了研究。最终选用粒径70 nm,质量分数为5%的磨料,去除速率可达到181 nm/min,表面粗糙度为9.1 nm,对今后铝栅CMP的研究提供了参考。

Defectivity control of aluminum chemical mechanical planarization in replacement metal gate process of MOSFET

The replacement metal gate（RMG） defectivity performance control is very challenging in high-k metal gate（HKMG） chemical mechanical polishing（CMP）. In this study, three major defect types, including fall-on particles, micro-scratch and corrosion have been investigated. The research studied the effects of polishing pad,pressure, rotating speed, flow rate and post-CMP cleaning on the three kinds of defect, which finally eliminated the defects and achieved good surface morphology. This study will provide an important reference value for the future research of aluminum metal gate CMP.

高k金属栅NMOSFET器件阈值电压调控方法

实现对器件阈值电压的有效调控是高k金属栅(HKMG)技术面临的一项重要挑战。TiAl薄膜作为n型金属氧化物半导体场效应晶体管(NMOSFET)的功函数层被广泛地应用于HKMG结构中以实现对器件阈值电压的调控。实验采用射频(RF)-直流(DC)磁控溅射的方式沉积TiAl薄膜,通过优化直流功率、射频功率和反应压强工艺参数,实现了对薄膜Ti/Al原子比率的调节,提高了Ti/Al原子比率分布均匀度。基于实验结果,采用后栅工艺流程制造HKMG NMOSFET,讨论不同的Ti/Al原子比率和TiAl层厚度对NMOSFET阈值电压的影响。Ti/Al原子比率增大10%,NMOSFET的阈值电压增加12.6%;TiAl层厚度增加2 nm,NMOSFET的阈值电压下降19.5%。这种方法已经被成功应用于HKMG器件的生产。

Dry etching of poly-Si/TaN/HfSiON gate stack for advanced complementary metal-oxide-semiconductor devices

A novel dry etching process of a poly-Si/TaN/HfSiON gate stack for advanced complementary metal-oxide-semiconductor（CMOS） devices is investigated.Our strategy to process a poly-Si/TaN/HfSiON gate stack is that each layer of gate stack is selectively etched with a vertical profile.First,a three-step plasma etching process is developed to get a vertical poly-Si profile and a reliable etch-stop on a TaN metal gate.Then different BCl_3-based plasmas are applied to etch the TaN metal gate and find that BCl_3/Cl_2/O_2/Ar plasma is a suitable choice to get a vertical TaN profile.Moreover,considering that Cl_2 almost has no selectivity to Si substrate, BCl_3/Ar plasma is applied to etch HfSiON dielectric to improve the selectivity to Si substrate after the TaN metal gate is vertically etched off by the optimized BCl_3/Cl_2/O_2/Ar plasma.Finally,we have succeeded in etching a poly-Si/TaN/HfSiON stack with a vertical profile and almost no Si loss utilizing these new etching technologies.

Energy distribution extraction of negative charges responsible for positive bias temperature instability

A new method is proposed to extract the energy distribution of negative charges, which results from electron trapping by traps in the gate stack of n MOSFET during positive bias temperature instability（PBTI） stress based on the recovery measurement. In our case, the extracted energy distribution of negative charges shows an obvious dependence on energy,and the energy level of the largest energy density of negative charges is 0.01 eV above the conduction band of silicon. The charge energy distribution below that energy level shows strong dependence on the stress voltage.

Structure design and film process optimization for metal-gate stress in 20 nm nMOS devices

The optimizations to metal gate structure and film process were extensively investigated for great metalgate stress（MGS） in 20 nm high-k/metal-gate-last（HKVMG-last） nMOS devices.The characteristics of advanced MGS technologies on device performances were studied through a process and device simulation by TCAD tools. The metal gate electrode with different stress values（0 to—6 GPa） was implemented in the device simulation along with other traditional process-induced-strain（PIS） technologies like e-SiC and nitride capping layer.The MGS demonstrated a great enhancing effect on channel carriers transporting in the device as device pitch scaling down.In addition,the novel structure for a tilted gate electrode was proposed and relationships between the tilt angle and channel stress were investigated.Also with a new method of fully stressed replacement metal gate（FSRMG） and using plane-shape-HfO to substitute U-shape-HfO,the effect of MGS was improved.For greater film stress in the metal gate,the process conditions for physical vapor deposition（PVD） TiN-x- were optimized.The maximum compressive stress of—6.5 GPa TiN_x was achieved with thinner film and greater RF power as well as about 6 sccm N ratio.

Novel devices and process for 32 nm CMOS technology and beyond

The development of next 32 nm generation and below needs innovations on not only device structures, but also fabrication techniques and material selections. Among those promising technologies, new gate structures as high-κ gate dielectric and metal gate, strain channel carrier mobility enhancement technology, and novel non-planar MOSFET structures are all possible candidate technologies. In this paper, we will specify our discussion on the research progress of high-κ-metal gate and non-planar MOSFET-technologies that are suitable to 32 nm technology node and beyond.