A Survey on Performance Optimization of High-Level Synthesis Tools

Field-programmable gate arrays(FPGAs)have recently evolved as a valuable component of the heterogeneous computing.The register transfer level(RTL)design flows demand the designers to be experienced in hardware,resulting in a possible failure of time-to-market.High-level synthesis(HLS)permits designers to work at a higher level of abstraction through synthesizing high-level language programs to RTL descriptions.This provides a promising approach to solve these problems.However,the performance of HLS tools still has limitations.For example,designers remain exposed to various aspects of hardware design,development cycles are still time consuming,and the quality of results(QoR)of HLS tools is far behind that of RTL flows.In this paper,we survey the literature published since 2014 focusing on the performance optimization of HLS tools.Compared with previous work,we extend the scope of the performance of HLS tools,and present a set of three-level evaluation criteria,covering from ease of use of the HLS tools to promotion on specific metrics of QoR.We also propose performance evaluation equations for describing the relation between the performance optimization and the QoR.We find that it needs more efforts on the ease of use for efficient HLS tools.We suggest that it is better to draw an analogy between the HLS development process and the embedded system design process,and to provide more elastic HLS methodology which integrates FPGAs virtual machines.

ON THE OPTIMIZATION OF VLSI ALLOCATION IN HIGH-LEVEL SYNTHESIS

Allocation is one of main tasks in the high-level synthesis. It includes module , functional unit allocation, storage allocation and interconnection allocation. This paper models the allocation problem as cluster analysis and applies a new algorithm, neighbor state transition (NST) algorithm, for cluster optimization. It is proved that the algorithm produces an asymptotically global optimal solution with the upper bound on the cost function (1 + O(1/n)2-ε)F*, When F" is the cost of the optimum solution, n is the problem size and e is a positive parameter arbitrarily close to zero. The numerical examples show that the NST algorithm produces better results compared to the other known methods.

A high-level synthesis based dual-module redundancy with multi-residue detection(DMR-MRD)fault-tolerant method for on-board processing satellite communication systems

On board processing(OBP) satellite systems have obtained more and more attentions in recent years because of their high efficiency and performance.However,the OBP transponders are very sensitive to the high energy particles in the space radiation environments.Single event upset(SEU)is one of the major radiation effects,which influences the satellite reliability greatly.Triple modular redundancy(TMR) is a classic and efficient method to mask SEUs.However,TMR uses three identical modules and a comparison logic,the circuit size becomes unacceptable,especially in the resource limited environments such as OBP systems.Considering that,a new SEU-tolerant method based on residue code and high-level synthesis(HLS) is proposed,and the new method is applied to FIR filters,which are typical structures in the OBP systems.The simulation results show that,for an applicable HLS scheduling scheme,area reduction can be reduced by 48.26%compared to TMR,while fault missing rate is 0.15%.

Synthesis of SrTiO_3 for immobilization of simulated HLW by SHS

Strontium titanate synroc samples were synthesized by self-propagating high-temperature synthesis （SHS）. Sr directly took part in the synthesis process. As a result, the loading content issue is basically resolved. The products were characterized by density, microhardness X-ray diffraction, and scanning electron microscopy （SEM/EDS）. The leaching rate was measured by the method of PCT （product consistency test）. The results indicate that the Sr^2＋-SrTiO3 compound is of high density, low leach rate and high stability and the synthesis process is feasible in technology and economy. It can be concluded that the strontium titanate synroc is a perfect material to immobilize HLW.

Synthesis of New Mannich Products Bearing Quinoline Nucleous Using Reusable Ionic Liquid and Antitubercular Evaluation

A series of Mannich products bearing quinoline nucleus was synthesized, characterized, and evaluated for their in vitro antitubercular activity against Mycobacterium tuberculosis H37Rv. The results showed that compounds 4b, and 4d found most active with percentage inhibition of 95, and 96, respectively, at minimum inhibitory concentration (MIC) of >6.25 μg/mL, among the synthesized compounds. Whereas, compounds 4a, 4c, 4e, and 4f exhibited considerable antitubercular activity with percentage inhibition of 71, 79, 55, and 68, respectively, at MIC of >6.25 μg/mL. The structures of synthesized compounds were elucidated by various spectroscopic tools like IR, 1H NMR, 13C NMR, mass and elemental analysis.

DYNAMICS ANALYSIS OF SPECIAL STRUCTURE OF MILLING-HEAD MACHINE TOOL

The milling-head machine tool is a sophisticated and high-quality machine tool of which the spindle system is made up of special multi-element structure. Two special mechanical configurations make the cutting performance of the machine tool decline. One is the milling head spindle supported on two sets of complex bearings. The mechanical dynamic rigidity of milling head structure is researched on designed digital prototype with finite element analysis（FEA） and modal synthesis analysis （ MSA ） for identifying the weak structures. The other is the ram structure hanging on milling head. The structure is researched to get dynamic performance on cutting at different ram extending positions. The analysis results on spindle and ram are used to improve the mechanical configurations and structure in design. The machine tool is built up with modified structure and gets better dynamic rigidity than it was before.

In-situ Fabricated TiB_2 Particle-whisker Synergistically Toughened Ti(C,N)-based Ceramic Cutting Tool Material

The mechanical properties of ceramic cutting tool materials can be modified by introducing proper content of nanoparticles or whiskers.However,the process of adding whiskers or nanoparticles has the disadvantages of high cost and health hazard as well as the agglomeration;although a new in-situ two-step sintering process can solve the above problems to some extent,yet the problems of low conversion ratio of the raw materials and the abnormal grain growth exist in this process.In this paper,an in-situ one-step synthesis technology is proposed,which means the growth of whiskers or nanoparticles and the sintering of the compact can be accomplished by one time in furnace.A kind of Ti（C,N）-based ceramic cutting tool material synergistically toughened by TiB_2 particles and whiskers is fabricated with this new process.The phase compositions,relationships between microstructure and mechanical properties as well as the toughening mechanisms are analyzed by means of X-ray diffraction（XRD）and scanning electron microscopy（SEM）.The composite which is sintered under a pressure of 32 MPa at a temperature of 1700℃in vacuum holding for 60 min can get the optimal mechanical properties.Its flexural strength,fracture toughness and Vickers hardness are 540 MPa,7.81 MPa·m（1/2）and 20.42 GPa,respectively.The composite has relatively high density,and the in-situ synthesized TiB_2 whiskers have good surface integrity,which is beneficial for the improvement of the fracture toughness.It is concluded that the main toughening mechanisms of the present composite are whiskers pulling-out and crack deflection induced by whiskers,crack bridging by whiskers/particles and multi-scale particles synergistically toughening.This study proposes an in-situ one-step synthesis technology which can be well used for fabricating particles and whiskers synergistically toughened ceramic tool materials.

METHOD OF HIGH-LEVEL TECHNOLOGY MAPPING BASED ON KNOWLEDGE(RULE)

This paper studies the linkage problem between the result of high-level synthesis and back-end technology, presents a method of high-level technology mapping based on knowl edge, and studies deeply all of its important links such as knowledge representation, knowledge utility and knowledge acquisition. It includes: (1) present a kind of expanded production about knowledge of circuit structure; (2) present a VHDL-based method to acquire knowledge of tech nology mapping; (3) provide solution control strategy and algorithm of knowledge utility; (4)present a half-automatic maintenance method, which can find redundance and contradiction of knowledge base; (5) present a practical method to embed the algorithm into knowledge system to decrease complexity of knowledge base. A system has been developed and linked with three kinds of technologies, so verified the work of this paper.

SF^2HDL： A Computational Tool of State Transition Diagram Translation

The lack of standard to electronic circuits modeling made possible the development of many tools and modeling languages for electronic circuits. In this way, several tools to be used on different descriptions stage of the designs are necessary. This paper presents a tool called SF^2HDL （Stateflow to Hardware Description Language or State Transition Table） that translates a finite state machine on state transition diagram representation, described by Stateflow tool, into an input file standard for TABELA program or into a file behavioral VHDL （Very High Speed Integrated Circuits Hardware Description Language） directly. The TABELA program was used to optimization this finite state machine. After that, the TAB2VHDL program was used to generate the VHDL code on register transfer level, what permits comparisons with results obtained by synthesis. The finite state machine must be described by Mealy model and the user can describe the machine on high level abstraction using all Simulink supports. The tool was very efficient on computational cost and it made translation of several cases, for the two VHDL description models. Every state machine translated was simulated and implemented on device EP2C20F484C7 using Quartus II environment.

Dimensional Synthesis Design of Novel Parallel Machine Tool

This paper presents dimensional synthesis design theory for a novel planar 3-DOF (degrees of freedom) parallel machine tool. Closed-form solutions are developed for both the inverse and direct kinematics. The formulation of the dexterity and the definitions of the theoretical workspace and the valid workspace are used to analyze the effects of the design parameters on the dexterity and workspace. The analysis results are used to propose an approach to satisfy the platform motion requirement while realizing orientation capability, dexterity and valid workspace. A design example is given to illustrate the effectiveness of this approach.

Register Allocation Algorithm for High-Level Circuit Synthesis for Improved Testability

Register allocation in high-level circuit synthesis is important not only for reducing area, delay, and power overheads, but also for improving the testability of the synthesized circuits. This paper presents an improved register allocation algorithm that improves the testability called weighted graph-based balanced register allocation for high-level circuit synthesis. The controllability and observability of the registers and the self-loop elimination are analyzed to form a weighted conflict graph, where the weight of the edge between two nodes denotes the tendency of the two variables to share the same register. Then the modified desaturation algorithm is used to dynamically modify the weights to obtain a final balanced register allocation which improves the testability of the synthesized circuits a higher fault coverage than other algorithms with Tests on some benchmarks show that the algorithm gives less area overhead and even less time delay.

The RTL Binding and Mapping Approach of VHDL High-Level Synthesis System HLS/BIT

This paper describes a VHDL high-level synthesis system HLS/BIT with emphasis on its register-transfer level (RTL) binding and technology mapping subsystem. In more detail, the component instantiation mechanism and the knowledge-driven approach to RTL technology mapping are also presented.

A Novel Testability-Oriented Data Path Scheduling Scheme in High-Level Synthesis

Scheduling is an important step in high-level synthesis and can greatly influence the testability of the synthesized circuits. This paper presents an efficient testability-improved data path scheduling scheme based on mobility scheduling, in which the scheduling begins from the operation with least mobility. In our data path scheduling scheme, the lifetimes of the I/O variables are made as short as possible to enlarge the possibility of the intermediate variables being allocated to the I/O registers. In this way, the controllability/observability of the intermediate variables can be improved. Combined with a weighted graph-based register allocation method, this scheme can obtain better testability. Experimental results on some benchmarks and example circuits show that the proposed scheme can get higher fault coverage compared with other scheduling schemes at little area overhead and even less time delay.

LP-LDPC:Three-Level Parallel FPGA Architecture for Fast Prototyping of LDPC Decoder Using High-Level Synthesis

Low-Density Parity-heck Codes(LDPC)with excellent error-correction capabilities have been widely used in both data communication and storage fields,to construct reliable cyber-physical systems that are resilient to real-world noises.Fast prototyping field-programmable gate array(FPGA)-based decoder is essential to achieve high decoding performance while accelerating the development process.This paper proposes a three-level parallel architecture,TLP-LDPC,to achieve high throughput by fully exploiting the characteristics of both LDPC and underlying hardware while effectively scaling to large-size FPGA platforms.The three-level parallel architecture contains a low-level decoding unit,a mid-level multi-unit decoding core,and a high-level multi-core decoder.The low-level decoding unit is a basic LDPC computation component that effectively combines the features of the LDPC algorithm and hardware with the specific structure(e.g.,Look-Up-Table,LUT)of the FPGA and eliminates potential data conflicts.The mid-level decoding core integrates the input/output and multiple decoding units in a well-balancing pipelined fashion.The top-level multi-core architecture conveniently makes full use of board-level resources to improve the overall throughput.We develop an LDPC C++code with dedicated pragmas and leverage HLS tools to implement the TLP-LDPC architecture.Experimental results show that TLP-LDPC achieves 9.63 Gbps end-to-end decoding throughput on a Xilinx Alveo U50 platform,3.9x higher than existing HLS-based FPGA implementations.

可重构机床的模块化设计

可重构机床是可重构制造系统的重要组成部分 ,其设计方法是实现制造过程可重构的关键。本文对可重构机床的模块化设计方法进行了探讨 ,系统分析了可重构机床区别于传统机床的模块化设计方法和特点。针对可重构机床设计任务驱动、运动重构的需求 ,在对机床结构进行拓扑图抽象描述的基础上 ,基于螺旋理论对加工任务进行运动分析和机床运动建模 ,提出了一种可重构机床模块化综合的设计方法 ,以生成满足加工任务运动需求的机床重构可行方案。

甲基辛基二甲氧基硅烷的合成研究

以辛烯和甲基二甲氧基氢硅为反应物,甲苯为溶剂,铂络合物为催化剂,在一定温度下生成甲基辛基二甲氧基硅烷。并讨论了反应温度、反应物的摩尔比、溶剂的用量、反应时间对产率的影响。

并联机床进给传动系统弹性动力学建模方法研究

利用动态子结构法研究一种外副驱动可实现 3平动自由度并联机床进给系统的动力学建模方法。首先将原系统分解成若干子结构 ,在建立各自动力学模型后 ,借助边界条件经综合得到系统的动力学方程。该方法手续简便、计算效率高 ,便于讨论结构参数对低阶模态的影响规律 ,故为这类复杂时变系统的动刚度预估和动态设计奠定了坚实的理论基础。

用蒙特卡洛法进行6腿并联机床精度综合

在综合考虑零部件制造公差和运动副配合间隙的基础上 ,利用蒙特卡洛法对 6腿并联机床进行了精度综合。结果表明 ,这种方法简便直观 ,易于编程。

串并混联机床几何误差建模与实验

以多体系统理论为基础,研究了串并混联机床的几何误差。考虑各运动轴的定位误差、直线度误差、角度误差以及垂直度误差的综合作用,提出一种机床综合误差建模方法。通过对该机床各部件拓扑结构进行抽象化描述,推导出混联机床两相邻体间相对运动的特征矩阵,建立了混联机床的整机综合误差模型。利用激光干涉仪对X、Y轴多项几何误差进行测量,并将测得的几何误差带入综合误差模型。通过分析所测的各项几何误差以及综合误差分布和演变规律发现:X、Y轴定位误差对整机综合误差的影响最大,直线度误差次之,角度误差影响最小;在精度要求不高的情况下,角度误差对综合误差的影响可忽略。

准双曲面齿轮的优化切齿设计

本文应用Litvin的局部综合方法进行了准双曲面齿轮切齿设计的推导。通过一次计算便能获得HGM和HGT加工的准双曲面齿轮的全部切齿参数。并且在啮合区位置、接触椭圆尺寸、接触轨迹方向和传动误差的形状、幅值等啮合质量方面严格符合预先给定的要求,为简化准双曲面齿轮的加工试切及保证传动质量提供了条件。