In high-level synthesis of VLSI circuits, good lower bound prediction canefficiently narrow down the large space of possible designs. Previous approaches predict the lowerbound by relaxing or even ignoring the precede...In high-level synthesis of VLSI circuits, good lower bound prediction canefficiently narrow down the large space of possible designs. Previous approaches predict the lowerbound by relaxing or even ignoring the precedence constraints of the data flow graph (DFG), andresult in inaccuracy of the lower bound. The loop folding and conditional branch were also notconsidered. In this paper, a new stepwise refinement algorithm is proposed, which takesconsideration of precedence constraints of the DFG to estimate the lower bound of hardware resourcesunder time constraints. Processing techniques to handle multi-cycle, chaining, pipelining, as wellas loop folding and mutual exclusion among conditional branches are also incorporated in thealgorithm. Experimental results show that the algorithm can produce a very tight and close tooptimal lower bound in reasonable computation time.展开更多
文摘In high-level synthesis of VLSI circuits, good lower bound prediction canefficiently narrow down the large space of possible designs. Previous approaches predict the lowerbound by relaxing or even ignoring the precedence constraints of the data flow graph (DFG), andresult in inaccuracy of the lower bound. The loop folding and conditional branch were also notconsidered. In this paper, a new stepwise refinement algorithm is proposed, which takesconsideration of precedence constraints of the DFG to estimate the lower bound of hardware resourcesunder time constraints. Processing techniques to handle multi-cycle, chaining, pipelining, as wellas loop folding and mutual exclusion among conditional branches are also incorporated in thealgorithm. Experimental results show that the algorithm can produce a very tight and close tooptimal lower bound in reasonable computation time.
