The time-interleaved analog-to-digital conversion(TIADC)technique is an effective method for increasing the sampling rate in a waveform digitization system.In this study,a 20-Gsps TIADC system was designed.A wide-band...The time-interleaved analog-to-digital conversion(TIADC)technique is an effective method for increasing the sampling rate in a waveform digitization system.In this study,a 20-Gsps TIADC system was designed.A wide-bandwidth performance was achieved by optimizing the analog circuits,and a sufficient effective number of bits(ENOB)performance guaranteed using the perfect reconstruction algorithm for mismatch error correction.The proposed system was verified by tests,and the results indicated that a-3 dB bandwidth of 6 GHz and the ENOB performance of 8.7 bits at 1 GHz and 7.6 bits at6 GHz were successfully achieved.展开更多
This paper analyzes the power consumption and delay mechanisms of the successive-approximation （SA） logic of a typical asynchronous SAR ADC, and provides strategies to reduce both of them. Following these strategies...This paper analyzes the power consumption and delay mechanisms of the successive-approximation （SA） logic of a typical asynchronous SAR ADC, and provides strategies to reduce both of them. Following these strategies, a unique direct-pass SA logic is proposed based on a full-swing once-triggered DFF and a self-locking tri-state gate. The unnecessary internal switching power of a typical TSPC DFF, which is commonly used in the SA logic, is avoided. The delay of the ready detector as well as the sequencer is removed from the critical path. A prototype SAR ADC based on the proposed SA logic is fabricated in 130 nm CMOS. It achieves a peak SNDR of 56.3 dB at 1.2 V supply and 65 MS/s sampling rate, and has a total power consumption of 555 μW, while the digital part consumes only 203μW.展开更多
基金supported in part by the National Natural Science Foundation of China(No.11675173)the Youth Innovation Promotion Association CASthe CAS Center for Excellence in Particle Physics(CCEPP)。
文摘The time-interleaved analog-to-digital conversion(TIADC)technique is an effective method for increasing the sampling rate in a waveform digitization system.In this study,a 20-Gsps TIADC system was designed.A wide-bandwidth performance was achieved by optimizing the analog circuits,and a sufficient effective number of bits(ENOB)performance guaranteed using the perfect reconstruction algorithm for mismatch error correction.The proposed system was verified by tests,and the results indicated that a-3 dB bandwidth of 6 GHz and the ENOB performance of 8.7 bits at 1 GHz and 7.6 bits at6 GHz were successfully achieved.
基金supported by the National Natural Science Foundation of China(Nos.61204033,61331015)the Fundamental Research Funds for the Central Universities(No.WK2100230015)the Funds of Science and Technology on Analog Integrated Circuit Laboratory(No.9140C090111150C09041)
文摘This paper analyzes the power consumption and delay mechanisms of the successive-approximation （SA） logic of a typical asynchronous SAR ADC, and provides strategies to reduce both of them. Following these strategies, a unique direct-pass SA logic is proposed based on a full-swing once-triggered DFF and a self-locking tri-state gate. The unnecessary internal switching power of a typical TSPC DFF, which is commonly used in the SA logic, is avoided. The delay of the ready detector as well as the sequencer is removed from the critical path. A prototype SAR ADC based on the proposed SA logic is fabricated in 130 nm CMOS. It achieves a peak SNDR of 56.3 dB at 1.2 V supply and 65 MS/s sampling rate, and has a total power consumption of 555 μW, while the digital part consumes only 203μW.
