By applying switch-signal theory, the interaction between MOS transmission switch-ing transistor and current signal in current-mode CMOS circuits is analyzed, and the theory oftransmission current-switches which is su...By applying switch-signal theory, the interaction between MOS transmission switch-ing transistor and current signal in current-mode CMOS circuits is analyzed, and the theory oftransmission current-switches which is suitable to current-mode CMOS circuits is proposed. Thecircuits, such as ternary full-adder etc., designed by using this theory have simpler circuit struc-tures and correct logic functions. It is confirmed that this theory is efficient in guiding the logicdesign of current-mode CMOS circuits at switch level.展开更多
Single-Pole Double-Throw （SPDT） broadband switch has been designed in a 0.25gm Complementary Metal Oxide Semiconductor （CMOS） process. To optimize the performance of isolation and insertion loss, based on normal d...Single-Pole Double-Throw （SPDT） broadband switch has been designed in a 0.25gm Complementary Metal Oxide Semiconductor （CMOS） process. To optimize the performance of isolation and insertion loss, based on normal design, the effects of Gate Series Resistances （GSR） on insertion loss and switching time are analyzed for the first time. The compatible GSRs are chosen by the analyses. The fabricated chips were tested and the results show the switch isolation from DC （Direct Current） to 1GHz exhibits 55dB and insertion loss lower than 2.1 dB.展开更多
提出了应用0.13μm CMOS工艺设计的具有高隔离度的Ka波段单刀双掷（Single Pole Double Throw,SPDT）开关。测试结果显示,在Ka波段此单片开关插损为2.7~3.7 d B,在35 GHz时测得的输入1dB压缩点（P_（-1dB））为8d Bm。通过使用并联NMOS...提出了应用0.13μm CMOS工艺设计的具有高隔离度的Ka波段单刀双掷（Single Pole Double Throw,SPDT）开关。测试结果显示,在Ka波段此单片开关插损为2.7~3.7 d B,在35 GHz时测得的输入1dB压缩点（P_（-1dB））为8d Bm。通过使用并联NMOS晶体管的拓扑结构并且使用高Q值的匹配网络,测得的开关在30~45 GHz有33~51 d B的隔离度。此Ka波段单刀双掷开关芯片的核心面积（die）仅仅为160×180μm2。展开更多
基金Supported by National Natural Science Foundation of China
文摘By applying switch-signal theory, the interaction between MOS transmission switch-ing transistor and current signal in current-mode CMOS circuits is analyzed, and the theory oftransmission current-switches which is suitable to current-mode CMOS circuits is proposed. Thecircuits, such as ternary full-adder etc., designed by using this theory have simpler circuit struc-tures and correct logic functions. It is confirmed that this theory is efficient in guiding the logicdesign of current-mode CMOS circuits at switch level.
基金Partially supported by the National Natural Science Foundation of China (No.60501012).
文摘Single-Pole Double-Throw （SPDT） broadband switch has been designed in a 0.25gm Complementary Metal Oxide Semiconductor （CMOS） process. To optimize the performance of isolation and insertion loss, based on normal design, the effects of Gate Series Resistances （GSR） on insertion loss and switching time are analyzed for the first time. The compatible GSRs are chosen by the analyses. The fabricated chips were tested and the results show the switch isolation from DC （Direct Current） to 1GHz exhibits 55dB and insertion loss lower than 2.1 dB.
文摘提出了应用0.13μm CMOS工艺设计的具有高隔离度的Ka波段单刀双掷（Single Pole Double Throw,SPDT）开关。测试结果显示,在Ka波段此单片开关插损为2.7~3.7 d B,在35 GHz时测得的输入1dB压缩点（P_（-1dB））为8d Bm。通过使用并联NMOS晶体管的拓扑结构并且使用高Q值的匹配网络,测得的开关在30~45 GHz有33~51 d B的隔离度。此Ka波段单刀双掷开关芯片的核心面积（die）仅仅为160×180μm2。
