P-InGaN/p-GaN superlattices (SLs) are developed for a hole accumulation layer (HAL) of a blue light emitting diode (LED). Free hole concentration as high as 2.6× 1018 cm-3 is achieved by adjusting the Cp2Mg...P-InGaN/p-GaN superlattices (SLs) are developed for a hole accumulation layer (HAL) of a blue light emitting diode (LED). Free hole concentration as high as 2.6× 1018 cm-3 is achieved by adjusting the Cp2Mg flow rate during the growth of p-InGaN/p-GaN SLs. The p-InGaN/p-GaN SLs with appropriate Cp2Mg flow rates are then incorporated between the multi-quantum well and A1GaN electron blocking layer as an HAL, which leads to the enhancement of light output power by 29% at 200 mA, compared with the traditional LED without such SL HAL. Meanwhile, the efficiency droop is also effectively alleviated in the LED with the SL HAL. The improved performance is attributed to the increased hole injection efficiency, and the reduced electron leakage by inserting the p-type SL HAL.展开更多
A new partial SOI (silion-on-insulator) (PSOI) high voltage P-channel LDMOS (lateral double-diffused metal-oxide semiconductor) with an interface hole islands (HI) layer is proposed and its breakdown character...A new partial SOI (silion-on-insulator) (PSOI) high voltage P-channel LDMOS (lateral double-diffused metal-oxide semiconductor) with an interface hole islands (HI) layer is proposed and its breakdown characteristics are investigated theoretically. A high concentration of charges accumulate on the interface, whose density changes with the negative drain voltage, which increase the electric field (Er) in the dielectric buried oxide layer (BOX) and modulate the electric field in drift region . This results in the enhancement of the breakdown voltage (BV). The values of E1 and BV of an HI PSOI with a 2-~m thick SOI layer over a 1-~tm thick buried layer are 580V/~m and -582 V, respectively, compared with 81.5 V/p.m and -123 V of a conventional PSOI. Furthermore, the Si window also alleviates the self-heating effect (SHE). Moreover, in comparison with the conventional device, the proposed device exhibits low on-resistance.展开更多
An analytical model for a novel high voltage silicon-on-insulator device with composite-k (relative per mittivity) dielectric buried layer (CK SOl) is proposed. In this structure, the composite-k buried layer is c...An analytical model for a novel high voltage silicon-on-insulator device with composite-k (relative per mittivity) dielectric buried layer (CK SOl) is proposed. In this structure, the composite-k buried layer is composed by alternating Si3N4 and low-k (k = 2.65) dielectric in the lateral direction. Due to the composite-k buried layer, the breakdown voltage (BV) is improved both by the vertical and lateral direction. Taking the modulation effect of accumulated interface holes into account, an analytical model is developed. In the blocking state, the proposed model revealed the mechanism of hole accumulation above the Si3N4 buried layer and investigated the modulation effect of accumulated holes on the two-dimensional (2-D) potential and electric field distributions. This analytical model is verified by the simulation results. Compared with the low-k dielectric buried layer SO1 (LK SOl), simu lation results show that the BV for CK SOl is enhanced by 21% and the specific on-resistance is reduced by 32%, respectively.展开更多
文摘P-InGaN/p-GaN superlattices (SLs) are developed for a hole accumulation layer (HAL) of a blue light emitting diode (LED). Free hole concentration as high as 2.6× 1018 cm-3 is achieved by adjusting the Cp2Mg flow rate during the growth of p-InGaN/p-GaN SLs. The p-InGaN/p-GaN SLs with appropriate Cp2Mg flow rates are then incorporated between the multi-quantum well and A1GaN electron blocking layer as an HAL, which leads to the enhancement of light output power by 29% at 200 mA, compared with the traditional LED without such SL HAL. Meanwhile, the efficiency droop is also effectively alleviated in the LED with the SL HAL. The improved performance is attributed to the increased hole injection efficiency, and the reduced electron leakage by inserting the p-type SL HAL.
基金supported by the National Natural Science Foundation of China (Grant Nos. 60806025 and 60976060)the Funds of the National Laboratory of Analog Integrated Circuit (Grant No. 9140C0903070904)the Youth Teacher Foundation of the University of Electronic Science and Technology of China (Grant No. jx0721)
文摘A new partial SOI (silion-on-insulator) (PSOI) high voltage P-channel LDMOS (lateral double-diffused metal-oxide semiconductor) with an interface hole islands (HI) layer is proposed and its breakdown characteristics are investigated theoretically. A high concentration of charges accumulate on the interface, whose density changes with the negative drain voltage, which increase the electric field (Er) in the dielectric buried oxide layer (BOX) and modulate the electric field in drift region . This results in the enhancement of the breakdown voltage (BV). The values of E1 and BV of an HI PSOI with a 2-~m thick SOI layer over a 1-~tm thick buried layer are 580V/~m and -582 V, respectively, compared with 81.5 V/p.m and -123 V of a conventional PSOI. Furthermore, the Si window also alleviates the self-heating effect (SHE). Moreover, in comparison with the conventional device, the proposed device exhibits low on-resistance.
基金supported by the National Natural Science Foundation of China(Nos.60976060,61176069)the National Key Laboratory of Analogue Integrated Circuit,China(No.9140C090304110C0905)
文摘An analytical model for a novel high voltage silicon-on-insulator device with composite-k (relative per mittivity) dielectric buried layer (CK SOl) is proposed. In this structure, the composite-k buried layer is composed by alternating Si3N4 and low-k (k = 2.65) dielectric in the lateral direction. Due to the composite-k buried layer, the breakdown voltage (BV) is improved both by the vertical and lateral direction. Taking the modulation effect of accumulated interface holes into account, an analytical model is developed. In the blocking state, the proposed model revealed the mechanism of hole accumulation above the Si3N4 buried layer and investigated the modulation effect of accumulated holes on the two-dimensional (2-D) potential and electric field distributions. This analytical model is verified by the simulation results. Compared with the low-k dielectric buried layer SO1 (LK SOl), simu lation results show that the BV for CK SOl is enhanced by 21% and the specific on-resistance is reduced by 32%, respectively.