Hot carrier cooling in lead halide perovskites probed by two-pulse photovoltage correlation spectroscopy

The next-generation hot-carrier solar cells,which can overcome the Shockley-Queisser limit by harvesting excessenergy from hot carriers,are receiving increasing attention.Lead halide perovskite(LHP)materials are considered aspromising candidates due to their exceptional photovoltaic properties,good stability and low cost.The cooling rate of hotcarriers is a key parameter influencing the performance of hot-carrier solar cells.In this work,we successfully detected hotcarrier dynamics in operando LHP devices using the two-pulse photovoltage correlation technique.To enhance the signalto-noise ratio,we applied the delay-time modulation method instead of the traditional power modulation.This advancementallowed us to detect the intraband hot carrier cooling time for the organic LHP CH_(3)NH_(3)PbBr_(3),which is as short as 0.21 ps.In comparison,the inorganic Cs-based LHP CsPbBr_(3)exhibited a longer cooling time of around 0.59 ps due to differentphonon contributions.These results provide us new insights into the optimal design of hot-carrier solar cells and highlightthe potential of LHP materials in advancing solar cell technology.

1/f~γ Noise Characteristics of an n-MOSFET Under DC Hot Carrier Stress

The 1/fγ noise characteristic parameter Sfγ model in an n-MOSFET under DC hot carrier stress is studied. A method characterizing the MOSFET abilities of an anti-hot carrier with noise parameter Sfγ is presented. The hot carrier degradation effect of n-MOSFET in high-,mid-,and low gate stresses and its 1/fγ noise feature are studied. Experimental results agree well with the developed model.

Suppressing the hot carrier injection degradation rate in total ionizing dose effect hardened nMOSFETs

Annular gate nMOSFETs are frequently used in spaceborne integrated circuits due to their intrinsic good capability of resisting total ionizing dose （TID） effect. However, their capability of resisting the hot carrier effect （HCE） has also been proven to be very weak. In this paper, the reason why the annular gate nMOSFETs have good TID but bad HCE resistance is discussed in detail, and an improved design to locate the source contacts only along one side of the annular gate is used to weaken the HCE degradation. The good TID and HCE hardened capability of the design are verified by the experiments for I/O and core nMOSFETs in a 0.18 μm bulk CMOS technology. In addition, the shortcoming of this design is also discussed and the TID and the HCE characteristics of the replacers （the annular source nMOSFETs） are also studied to provide a possible alternative for the designers.

Positive Bias Temperature Instability and Hot Carrier Injection of Back Gate Ultra-thin-body In0.53Ga0.47As-on-Insulator n-Channel Metal-Oxide-Semiconductor Field-Effect Transistor

Ultra-thin-body （UTB） In0.53Ga0.47As-on-insulator （In0.53Ga0.47As-OI） structures with thicknesses of 8 and 15nm are realized by transferring epitaxially grown In0.53Ga0.47As layers to silicon substrates with 15-nmthick A12 03 as a buried oxide by using the direct wafer bonding method. Back gate n-channel metal-oxidesemiconductor field-effect transistors （nMOSFETs） are fabricated by using these In0.53Ga0.47As-OI structures with excellent electrical characteristics. Positive bias temperature instability （PBTI） and hot carrier injection （HCI） characterizations are performed for the In0.53Ga0.47As-OI nMOSFETs. It is confirmed that the In0.53Ga0.47 As-OI nMOSFETs with a thinner body thickness suffer from more severe degradations under both PBTI and HCr stresses. Moreover, the different evolutions of the threshold voltage and the saturation current of the UTB In0.53Ga0.47As-OI nMOSFETs may be due to the slow border traps.

Hot carrier injection degradation under dynamic stress

In this paper, we have studied hot carrier injection （HCI） different degradations are obtained from the experiment results. under alternant stress. Under different stress modes, The different alternate stresses can reduce or enhance the HC effect, which mainly depends on the latter condition of the stress cycle. In the stress mode A （DC stress with electron injection）, the degradation keeps increasing. In the stress modes B （DC stress and then stress with the smMlest gate injection） and C （DC stress and then stress with hole injection under Vg = 0 V and Vd = 1.8 V）, recovery appears in the second stress period. And in the stress mode D （DC stress and then stress with hole injection under Vg = -1.8 V and Vd = 1.8 V）, as the traps filled in by holes can be smaller or greater than the generated interface states, the continued degradation or recovery in different stress periods can be obtained.

Hot carrier degradation and a new lifetime prediction model in ultra-deep sub-micron pMOSFET

The hot carrier effect （HCE） of an ultra-deep sub-micron p-channel metal–oxide semiconductor field-effect transistor （pMOSFET） is investigated in this paper. Experiments indicate that the generation of positively charged interface states is the predominant mechanism in the case of the ultra-deep sub-micron pMOSFET. The relation of the pMOSFET hot carrier degradation to stress time （t）, channel width （W ）, channel length （L）, and stress voltage （Vd ） is then discussed. Based on the relation, a lifetime prediction model is proposed, which can predict the lifetime of the ultra-deep sub-micron pMOSFET accurately and reflect the influence of the factors on hot carrier degradation directly.

Impact of substrate injected hot electrons on hot carrier degradation in a 180-nm NMOSFET

Although hot carriers induced degradation of NMOSFETs has been studied for decades, the role of hot electron in this process is still debated. In this paper, the additional substrate hot electrons have been intentionally injected into the oxide layer to analyze tile role of hot electron in hot carrier degradation. The enhanced degradation and the decreased time exponent appear with the injected hot electrons increasing, the degradation increases from 21.80% to 62.00% and the time exponent decreases from 0.59 to 0.27 with Vb decreasing from 0 V to -4 V, at the same time, the recovery also becomes remarkable and which strongly depends on the post stress gate bias Vg. Based on the experimental results, more unrecovered interface traps are created by the additional injected hot electron from the breaking Si-H bond, but the oxide trapped negative charges do not increase after a rapid recovery.

Actions of negative bias temperature instability （NBTI） and hot carriers in ultra-deep submicron p-channel metal-oxide-semiconductor field-effect transistors （PMOSFETs）

Hot carrier injection （HCI） at high temperatures and different values of gate bias Vg has been performed in order to study the actions of negative bias temperature instability （NBTI） and hot carriers. Hot-carrier-stress-induced damage at Vg = Vd, where Vd is the voltage of the transistor drain, increases as temperature rises, contrary to conventional hot carrier behaviour, which is identified as being related to the NBTI. A comparison between the actions of NBTI and hot carriers at low and high gate voltages shows that the damage behaviours are quite different： the low gate voltage stress results in an increase in transconductance, while the NBTI-dominated high gate voltage and high temperature stress causes a decrease in transconductance. It is concluded that this can be a major source of hot carrier damage at elevated temperatures and high gate voltage stressing of p-channel metal-oxide-semiconductor field-effect transistors （PMOSFETs）. We demonstrate a novel mode of NBTI-enhanced hot carrier degradation in PMOSFETs. A novel method to decouple the actions of NBTI from that of hot carriers is also presented.

STUDY ON THE RELATION BETWEEN STRUCTURE AND HOT CARRIER EFFECT IMMUNITY FOR DEEP SUB-MICRON GROOVED GATE NMOSFET's

Grooved gate structure Metal-Oxide-Semiconductor (MOS) device is consideredas the most promising candidate used in deep and super-deep sub-micron region, for it cansuppress hot carrier effect and short channel effect deeply. Based on the hydrodynamic energytransport model, using two-dimensional device simulator Medici, the relation between structureparameters and hot carrier effect immunity for deep-sub-micron N-channel MOSFET's is studiedand compared with that of counterpart conventional planar device in this paper. The examinedstructure parameters include negative junction depth, concave corner and effective channel length.Simulation results show that grooved gate device can suppress hot carrier effect deeply even indeep sub-micron region. The studies also indicate that hot carrier effect is strongly influencedby the concave corner and channel length for grooved gate device. With the increase of concavecorner, the hot carrier effect in grooved gate MOSFET decreases sharply, and with the reducingof effective channel length, the hot carrier effect becomes large.

Characterization of hot carrier cooling and multiple exciton generation dynamics in PbS QDs using an improved transient grating technique

Multiple exciton generation （MEG） dynamics in colloidal PbS quantum dots （QDs） characterized with an im- proved transient grating （TG） technique will be reported. Only one peak soon after optical absorption and a fast decay within 1 ps can be observed in the TG kinetics when the photon energy of the pump light hv is smaller than 2.7Eg （Eg： band gap between LUMO and HOMO in the QDs）, which corresponds to hot carrier cooling. When hv is greater than 2.7Eg, however, after the initial peak, the TG signal decreases first and soon increases, and then a new peak appears at about 2 to 3 ps. The initial peak and the new peak correspond to hot carriers at the higher excited state and MEG at the lowest excited state, respectively. By proposing a theoretical model, we can calculate the hot carrier cooling time constant and MEG occurrence time constant quantitatively. When MEG does not happen for hv smaller than 2.7Eg, hot carrier cools with a time con- stant of 400 fs. When MEG occurs for hv larger than 2.7Eg, hot carrier cools with a time constant as small as 200 fs, while MEG occurs with a time constant of 600 fs. The detailed hot carrier cooling and MEG occurrence dynamics characterized in this work would shed light on the further understanding of MEG mechanism of various type of semiconductor QDs.

Effect of Hot Carrier on Amplitude Modulation and Demodulation of Gaussian High Power Helicon Wave in Homogeneous Longitudinally Magnetized Strain Dependent Dielectric Material

In the present communication, the hydrodynamic model is used to investigate the amplitude modulation as well as demodulation of an electromagnetic wave of high power helicon pump wave into another helicon wave in strain dependent dielectric material incorporating carrier heating (CH) effects. The consideration of CH in modulation and demodulation is prime importance for the adding of new dimension in analysis of amplification of acoustic helicon wave. By using the dispersion relation, threshold pump electric filed and growth rate of unstable mode from the modulation and demodulation of the high power helicon wave well above from the threshold value will be discussed in the present analysis. The numerical analysis is applied to a strain dependent dielectric material, BaTiO3 at room temperature and irradiated with high power helicon wave of frequency 1.78 × 1014 Hz. This material is very sensitive to the pump intensities, therefore during studies, Gaussian shape of the helicon pump wave is considered during the propagation in stain dependent dielectric material and opto-acoustic wave in the form of Gaussian profile (ω0,κ0) is induced longitudinally along the crystallographic plane of BaTiO3. Its variation is caused by the available magnetic field (ωc), interaction length (z) and pulsed duration of interaction (τ). From the analysis of numerical results, the incorporation of CH effect can effectively modify the magnitude of modulation or demodulation of the amplitude of high power helicon laser wave through diffusion process. Not only the amplitude modulation and demodulation of the wave, the diffusion of the CH effectively modifies the growth rate of unstable mode of frequency in BaTiO3. The propagation of the threshold electric field shows the sinusoidal or complete Gaussian profile, whereas this profile is found to be completely lost in growth of unstable mode. It has also been seen that the growth rate is observed to be of the order of 108 - 1010 s-1 but from diffusion of carrier heating, and that its order is enhanced from 1010 - 1012 s-1 with the variation of the magnetized frequency from 1 to 2.5 × 1014 Hz.

Switchable PLL Frequency Synthesizer andHot Carrier Effects

In this paper, a new strategy of switchable CMOS phase-locked loop frequency synthesizer is proposed to increase its tuning range. The switchable PLL which integrates two phase-locked loops with different tuning frequencies are designed and fabricated in 0.5 μm n-well CMOS process. Cadence/Spectre simulations show that the frequency range of the switchable phased-locked loop is between 320 MHz to 1.15 GHz. The experimental results show that the RMS jitter of the phase-locked loop changes from 26 ps to 123 ps as output frequency varies. For 700 MHz carrier frequency, the phase noise of the phase-locked loop reaches as low as ?81 dBc/Hz at 10 kHz offset frequency and ?104 dBc/Hz at 1 MHz offset frequency. A device degradation model due to hot carrier effects has been used to analyze the jitter and phase noise performance in an open loop voltage-controlled oscillator. The oscillation frequency of the voltage-controlled oscillator decreases by approximately 100 to 200 MHz versus the bias voltage and the RMS jitter increases by 40 ps under different phase-locked loop output frequencies after 4 hours of stress time.

Tuning hot carrier transfer dynamics by perovskite surface modification

Understanding the role of perovskite surface passivators in hot carriers transfer dynamics is important to develop highly efficient perovskite solar cells(PSCs).In this work,we have designed and synthesized a naphthalimide-based organic small molecule(NCN)for perovskite surface defect passivator.We reveal that the introduction of NCN not only reduces the density of perovskite defect-state,but also promotes hot carriers(HCs)cooling in perovskite through the transient absorption spectroscopy measurements.Fast HCs cooling permits HCs transfer from perovskite layer into NCN layer,thus resulting in the decreased charge-carrier recombination in NCN-treated device.As expected,the power conversion efficiency(PCE)of PSCs with NCN is enhanced to 22.02%from 19.95%for the control device.The findings are relevant for developing highly efficient PSCs.

Evidence of abnormal hot carrier thermalization at van Hove singularity of twisted bilayer graphene

Interlayer twist evokes revolutionary changes to the optical and electronic properties of twisted bilayer graphene(TBG)for electronics,photonics and optoelectronics.Although the ground state responses in TBG have been vastly and clearly studied,the dynamic process of its photoexcited carrier states mainly remains elusive.Here,we unveil the photoexcited hot carrier dynamics in TBG by time-resolved ultrafast photoluminescence(PL)autocorrelation spectroscopy.We demonstrate the unconventional ultrafast PL emission between the van Hove singularities(VHSs)with a~4 times prolonged relaxation lifetime.This intriguing photoexcited carrier behavior is ascribed to the abnormal hot carrier thermalization brought by bottleneck effects at VHSs and interlayer charge distribution process.Our study on hot carrier dynamics in TBG offers new insights into the excited states and correlated physics of graphene twistronics systems.

Plasmon-induced hot carrier dynamics and utilization

Plasmonics has aroused tremendous interest in photophysics,nanophotonics,and metamaterials.The extreme field concentration of plasmonics offers the ultimate spatial and temporal light control,single-particle detection,and optical modulation.Plasmon decay of metal nanostructures into hot carriers extends the application into photocatalysis,photodetectors,photovoltaics,and ultrafast nanooptics.The generated hot electron–hole pairs are transferred into adjacent dielectrics,well known to be more efficient than the hot carrier generation in dielectrics by direct photoexcitations.However,plasmon-induced hot-carrier-based devices are far from practical applications due to the low quantum yield of hot carrier extraction.Emergent challenges include low hot carrier generation efficiency in metals,rapid energy loss of hot carriers,and severe charge recombination at the metal/dielectric interface.In this review,we provide a fundamental insight into the hot carrier generation,transport,injection,and diffusion into dielectrics based on the steady-state and time-resolved spectroscopic studies as well as theoretical calculations.Strategies to enhance hot carrier generation in metals and electron transfer into dielectrics are discussed in detail.Then,applications based on hot carrier transfer are introduced briefly.Finally,we provide our suggestions on future research endeavors.We believe this review will provide a valuable overall physical picture of plasmon-induced hot carrier applications for researchers.

Unified Degradation Model in Low Gate Voltage Range During Hot-Carrier Stressing of p-MOS Transistors

Hot carrier effects of p MOSFETs with different oxide thicknesses are studied in low gate voltage range.All electrical parameters follow a power law relationship with stress time,but degradation slope is dependent on gate voltage.For the devices with thicker oxides,saturated drain current degradation has a close relationship with the product of gate current and electron fluence.For small dimensional devices,saturated drain current degradation has a close relationship with the electron fluence.This degradation model is valid for p MOSFETs with 0 25μm channel length and different gate oxide thicknesses.

Experimental Evidence of Interface-Trap-Related SILC in Ultrathin (4nm- and 2.5nm-Thick) n-MOSFET and p-MOSFET Under Hot-Carrier Stress

Stress-induced leakage current (SILC) of ultrathin gate oxide is investigated by observing the generation of interface traps for n-MOSFET and p-MOSFET under hot-carrier stress.It is found experimentally that there is linear correlation between the generation of interface traps and SILC for both types of MOSFET with different channel lengths (including 1,0.5,0.275,and 0.135μm) and different gate oxide thickness (4nm and 2.5nm).These experimental evidences show that the SILC has a strong dependence on interface traps.

New Forward Gated-Diode Technique for Separating Front Gate Interface- from Oxide-Traps Induced by Hot-Carrier-Stress in SOI-NMOSFETs

The front gate interface and oxide traps induced by hot carrier stress in SOI NMOSFETs are studied.Based on a new forward gated diode technique,the R G current originating from the front interface traps is measured,and then the densities of the interface and oxide traps are separated independently.The experimental results show that the hot carrier stress of front channel not only results in the strong generation of the front interface traps,but also in the significant oxide traps.These two kinds of traps have similar characteristic in increasing with the hot carrier stress time.This analysis allows one to obtain a clear physical picture of the effects of the hot carrier stress on the generating of interface and oxide traps,which help to understand the degradation and reliability of the SOI MOSFETs.

Oxide Thickness Effects on n-MOSFETs Under On-State Hot-Carrier Stress

Hot carrier induced (HCI) degradation of surface channel n MOSFETs with different oxide thicknesses is investigated under maximum substrate current condition.Results show that the key parameters m and n of Hu's lifetime prediction model have a close relationship with oxide thickness.Furthermore,a linear relationship is found between m and n .Based on this result,the lifetime prediction model can be expended to the device with thinner oxides.

Layout and process hot carrier optimization of HV-nLEDMOS transistor

Two layout and process key parameters for improving high voltage nLEDMOS （n-type lateral extended drain MOS） transistor hot carrier performance have been identified. Increasing the space between Hv-pwell and n-drift region and reducing the n-drift implant dose can dramatically reduce the device hot carder degradations, for the maximum impact ionization rate near the Bird Beak decreases or its location moves away from the Si/SiO2 interface. This conclusion has been analyzed in detail by using the MEDICI simulator and it is also confirmed by the test results.