Multilevel optoelectronic hybrid memory based on N-doped Ge_(2)Sb_(2)Te_(5)film with low resistance drift and ultrafast speed

Multilevel phase-change memory is an attractive technology to increase storage capacity and density owing to its high-speed,scalable and non-volatile characteristics.However,the contradiction between thermal stability and operation speed is one of key factors to restrain the development of phase-change memory.Here,N-doped Ge_(2)Sb_(2)Te_(5)-based optoelectronic hybrid memory is proposed to simultaneously implement high thermal stability and ultrafast operation speed.The picosecond laser is adopted to write/erase information based on reversible phase transition characteristics whereas the resistance is detected to perform information readout.Results show that when N content is 27.4 at.%,N-doped Ge_(2)Sb_(2)Te_(5)film possesses high ten-year data retention temperature of 175℃and low resistance drift coefficient of 0.00024 at 85℃,0.00170 at 120℃,and 0.00249 at 150℃,respectively,owing to the formation of Ge–N,Sb–N,and Te–N bonds.The SET/RESET operation speeds of the film reach 520 ps/13 ps.In parallel,the reversible switching cycle of the corresponding device is realized with the resistance ratio of three orders of magnitude.Four-level reversible resistance states induced by various crystallization degrees are also obtained together with low resistance drift coefficients.Therefore,the N-doped Ge_(2)Sb_(2)Te_(5)thin film is a promising phase-change material for ultrafast multilevel optoelectronic hybrid storage.

A hybrid memory architecture supporting fine-grained data migration

Hybrid memory systems composed of dynamic random access memory(DRAM)and Non-volatile memory(NVM)often exploit page migration technologies to fully take the advantages of different memory media.Most previous proposals usually migrate data at a granularity of 4 KB pages,and thus waste memory bandwidth and DRAM resource.In this paper,we propose Mocha,a non-hierarchical architecture that organizes DRAM and NVM in a flat address space physically,but manages them in a cache/memory hierarchy.Since the commercial NVM device-Intel Optane DC Persistent Memory Modules(DCPMM)actually access the physical media at a granularity of 256 bytes(an Optane block),we manage the DRAM cache at the 256-byte size to adapt to this feature of Optane.This design not only enables fine-grained data migration and management for the DRAM cache,but also avoids write amplification for Intel Optane DCPMM.We also create an Indirect Address Cache(IAC)in Hybrid Memory Controller(HMC)and propose a reverse address mapping table in the DRAM to speed up address translation and cache replacement.Moreover,we exploit a utility-based caching mechanism to filter cold blocks in the NVM,and further improve the efficiency of the DRAM cache.We implement Mocha in an architectural simulator.Experimental results show that Mocha can improve application performance by 8.2%on average(up to 24.6%),reduce 6.9%energy consumption and 25.9%data migration traffic on average,compared with a typical hybrid memory architecture-HSCC.

Power-Aware Data Management Based on Hybrid RAM-NVM Memory for Smart Bracelet

Wearable devices become popular because they can help people observe health condition.The battery life is the critical problem for wearable devices. The non-volatile memory(NVM) attracts attention in recent years because of its fast reading and writing speed, high density, persistence, and especially low idle power. With its low idle power consumption,NVM can be applied in wearable devices to prolong the battery lifetime such as smart bracelet. However, NVM has higher write power consumption than dynamic random access memory(DRAM). In this paper, we assume to use hybrid random access memory(RAM)and NVM architecture for the smart bracelet system.This paper presents a data management algorithm named bracelet power-aware data management(BPADM) based on the architecture. The BPADM can estimate the power consumption according to the memory access, such as sampling rate of data, and then determine the data should be stored in NVM or DRAM in order to satisfy low power. The experimental results show BPADM can reduce power consumption effectively for bracelet in normal and sleeping modes.

Resource abstraction and data placement for distributed hybrid memory pool

Emerging byte-addressable non-volatile memory(NVM)technologies offer higher density and lower cost than DRAM,at the expense of lower performance and limited write endurance.There have been many studies on hybrid NVM/DRAM memory management in a single physical server.However,it is still an open problem on how to manage hybrid memories efficiently in a distributed environment.This paper proposes Alloy,a memory resource abstraction and data placement strategy for an RDMA-enabled distributed hybrid memory pool(DHMP).Alloy provides simple APIs for applications to utilize DRAM or NVM resource in the DHMP,without being aware of the hardware details of the DHMP.We propose a hotness-aware data placement scheme,which combines hot data migration,data replication and write merging together to improve application performance and reduce the cost of DRAM.We evaluate Alloy with several micro-benchmark workloads and public benchmark workloads.Experimental results show that Alloy can significantly reduce the DRAM usage in the DHMP by up to 95%,while reducing the total memory access time by up to 57%compared with the state-of-the-art approaches.

Superpage-Friendly Page Table Design for Hybrid Memory Systems

Page migration has long been adopted in hybrid memory systems comprising dynamic random access memory(DRAM)and non-volatile memories(NVMs),to improve the system performance and energy efficiency.However,page migration introduces some side effects,such as more translation lookaside buffer(TLB)misses,breaking memory contiguity,and extra memory accesses due to page table updating.In this paper,we propose superpagefriendly page table called SuperPT to reduce the performance overhead of serving TLB misses.By leveraging a virtual hashed page table and a hybrid DRAM allocator,SuperPT performs address translations in a flexible and efficient way while still remaining the contiguity within the migrated pages.

A high-fidelity memory scheme for quantum data buses

A novel quantum memory scheme is proposed for quantum data buses in scalable quantum computers by using adjustable interaction. Our investigation focuses on a hybrid quantum system including coupled flux qubits and a nitrogen–vacancy center ensemble. In our scheme, the transmission and storage（retrieval） of quantum state are performed in two separated steps, which can be controlled by adjusting the coupling strength between the computing unit and the quantum memory. The scheme can be used not only to reduce the time of quantum state transmission, but also to increase the robustness of the system with respect to detuning caused by magnetic noises. In comparison with the previous memory scheme, about 80% of the transmission time is saved. Moreover, it is exemplified that in our scheme the fidelity could achieve 0.99 even when there exists detuning, while the one in the previous scheme is 0.75.

EXPONENTIAL STABILITY AND PERIODIC SOLUTION OF HYBRID BIDIRECTIONAL ASSOCIATIVE MEMORY NEURAL NETWORKS WITH DISCRETE DELAYS

In this paper, we study the existence, uniqueness, and the global exponential stability of the periodic solution and equilibrium of hybrid bidirectional associative memory neural networks with discrete delays. By ingeniously importing real parameters di > 0 (i = 1,2, …, n) which can be adjusted, making use of the Lyapunov functional method and some analysis techniques, some new sufficient conditions are established. Our results generalize and improve the related results in [9]. These conditions can be used both to design globally exponentially stable and periodical oscillatory hybrid bidirectional associative neural networks with discrete delays, and to enlarge the area of designing neural networks. Our work has important significance in related theory and its application.

A Survey of Non-Volatile Main Memory Technologies:State-of-the-Arts,Practices,and Future Directions

Non-Volatile Main Memories (NVMMs) have recently emerged as a promising technology for future memory systems. Generally, NVMMs have many desirable properties such as high density, byte-addressability, non-volatility, low cost, and energy efficiency, at the expense of high write latency, high write power consumption, and limited write endurance. NVMMs have become a competitive alternative of Dynamic Random Access Memory (DRAM), and will fundamentally change the landscape of memory systems. They bring many research opportunities as well as challenges on system architectural designs, memory management in operating systems (OSes), and programming models for hybrid memory systems. In this article, we revisit the landscape of emerging NVMM technologies, and then survey the state-of-the-art studies of NVMM technologies. We classify those studies with a taxonomy according to different dimensions such as memory architectures, data persistence, performance improvement, energy saving, and wear leveling. Second, to demonstrate the best practices in building NVMM systems, we introduce our recent work of hybrid memory system designs from the dimensions of architectures, systems, and applications. At last, we present our vision of future research directions of NVMMs and shed some light on design challenges and opportunities.