Pixel image lag in a 4-T CMOS image sensor is analyzed and simulated in a two-dimensional model.Strategies of reducing image lag are discussed from transfer gate channel threshold voltage doping adjustment,PPD N-type ...Pixel image lag in a 4-T CMOS image sensor is analyzed and simulated in a two-dimensional model.Strategies of reducing image lag are discussed from transfer gate channel threshold voltage doping adjustment,PPD N-type doping dose/implant tilt adjustment and transfer gate operation voltage adjustment for signal electron transfer.With the computer analysis tool ISE-TCAD,simulation results show that minimum image lag can be obtained at a pinned photodiode n-type doping dose of 7.0×10^12 cm^-2,an implant tilt of -2°,a transfer gate channel doping dose of 3.0×10^12 cm^-2 and an operation voltage of 3.4 V.The conclusions of this theoretical analysis can be a guideline for pixel design to improve the performance of 4-T CMOS image sensors.展开更多
In order to increase collection efficiency and eliminate image lag, multi n-type implants were introduced into the process of a pinned-photodiode. For the purpose of improving the collection efficiency, multi n-type i...In order to increase collection efficiency and eliminate image lag, multi n-type implants were introduced into the process of a pinned-photodiode. For the purpose of improving the collection efficiency, multi n-type implants with different implant energies were proposed, which expanded the vertical collection region. To reduce the image lag, a horizontal gradient doping concentration eliminating the potential barrier was also formed by multi n-type implants. The simulation result shows that the collection efficiency can be improved by about 10% in the long wavelength range and the density of the residual charge is reduced from 2.59 × 10^9 to 2.62 × 10^7 cm^-3.展开更多
基金supported by the National Natural Science Foundation of China(Nos.60806010,60976030)the Tianjin Innovation Special Funds for science and Technology,China(No.05FZZDGX00200)
文摘Pixel image lag in a 4-T CMOS image sensor is analyzed and simulated in a two-dimensional model.Strategies of reducing image lag are discussed from transfer gate channel threshold voltage doping adjustment,PPD N-type doping dose/implant tilt adjustment and transfer gate operation voltage adjustment for signal electron transfer.With the computer analysis tool ISE-TCAD,simulation results show that minimum image lag can be obtained at a pinned photodiode n-type doping dose of 7.0×10^12 cm^-2,an implant tilt of -2°,a transfer gate channel doping dose of 3.0×10^12 cm^-2 and an operation voltage of 3.4 V.The conclusions of this theoretical analysis can be a guideline for pixel design to improve the performance of 4-T CMOS image sensors.
基金Project supported by the National Natural Science Foundation of China(Nos.61036004,60976030)
文摘In order to increase collection efficiency and eliminate image lag, multi n-type implants were introduced into the process of a pinned-photodiode. For the purpose of improving the collection efficiency, multi n-type implants with different implant energies were proposed, which expanded the vertical collection region. To reduce the image lag, a horizontal gradient doping concentration eliminating the potential barrier was also formed by multi n-type implants. The simulation result shows that the collection efficiency can be improved by about 10% in the long wavelength range and the density of the residual charge is reduced from 2.59 × 10^9 to 2.62 × 10^7 cm^-3.
