A scheme for creating an arbitrary coherent superposition of two atomic states in serial multi-A-type system is proposed. This technique with the application of a control field is based on the existence of two degener...A scheme for creating an arbitrary coherent superposition of two atomic states in serial multi-A-type system is proposed. This technique with the application of a control field is based on the existence of two degenerate dark states and their interaction. The mixing of the dark states can be controlled by changing the relative delay time of the control pulse. One can get any desired superposition by changing the delay time of the control pulse.展开更多
针对惯导组件产品测试中多种信号的输出,设计一种基于FPGA惯导组件输出模拟系统;以FPGA芯片为核心,在Quartus II软件开发平台上使用Verilog语言进行编程然后生成原理图,设计DDS(direct digital synthesizer)信号发生器来输出48路脉冲信...针对惯导组件产品测试中多种信号的输出,设计一种基于FPGA惯导组件输出模拟系统;以FPGA芯片为核心,在Quartus II软件开发平台上使用Verilog语言进行编程然后生成原理图,设计DDS(direct digital synthesizer)信号发生器来输出48路脉冲信号,实现对4个惯导组件输出的48路脉冲信号模拟;在FPGA中采用Verilog硬件描述语言编写8串口发送代码生成原理图,实现对8个惯导组件输出8路串口数据的模拟;通过人机交互界面的按键和液晶对脉冲输出和串口发送的参数进行调节,实现脉冲输出和串口发送的设定;利用DDS技术设计48路脉冲较其他方法精度更高,利用FPGA的并行运算特点实现8路串口数据的并行发送;设计降低了各种测试信号连接时的复杂度,提高了测试信号的稳定度和惯导组件标定的效率。展开更多
文摘A scheme for creating an arbitrary coherent superposition of two atomic states in serial multi-A-type system is proposed. This technique with the application of a control field is based on the existence of two degenerate dark states and their interaction. The mixing of the dark states can be controlled by changing the relative delay time of the control pulse. One can get any desired superposition by changing the delay time of the control pulse.
文摘针对惯导组件产品测试中多种信号的输出,设计一种基于FPGA惯导组件输出模拟系统;以FPGA芯片为核心,在Quartus II软件开发平台上使用Verilog语言进行编程然后生成原理图,设计DDS(direct digital synthesizer)信号发生器来输出48路脉冲信号,实现对4个惯导组件输出的48路脉冲信号模拟;在FPGA中采用Verilog硬件描述语言编写8串口发送代码生成原理图,实现对8个惯导组件输出8路串口数据的模拟;通过人机交互界面的按键和液晶对脉冲输出和串口发送的参数进行调节,实现脉冲输出和串口发送的设定;利用DDS技术设计48路脉冲较其他方法精度更高,利用FPGA的并行运算特点实现8路串口数据的并行发送;设计降低了各种测试信号连接时的复杂度,提高了测试信号的稳定度和惯导组件标定的效率。