Pixelated non-volatile programmable photonic integrated circuits with 20-level intermediate states

Multi-level programmable photonic integrated circuits(PICs)and optical metasurfaces have gained widespread attention in many fields,such as neuromorphic photonics,opticalcommunications,and quantum information.In this paper,we propose pixelated programmable Si_(3)N_(4)PICs with record-high 20-level intermediate states at 785 nm wavelength.Such flexibility in phase or amplitude modulation is achieved by a programmable Sb_(2)S_(3)matrix,the footprint of whose elements can be as small as 1.2μm,limited only by the optical diffraction limit of anin-house developed pulsed laser writing system.We believe our work lays the foundation for laser-writing ultra-high-level(20 levels and even more)programmable photonic systems and metasurfaces based on phase change materials,which could catalyze diverse applications such as programmable neuromorphic photonics,biosensing,optical computing,photonic quantum computing,and reconfigurable metasurfaces.

Design of Gas Sensors Circuits with in-System Programmable Ddevices

In-system programmable devices are products that combined modern electronic techniques and semiconductor techniques.They are indispensable devices in designing modern circuits and systems.This paper presents two practical circuits designed with programmable devices and its design method.By introducing programmable devices into gas sensor circuits,we can further improve system reliability,stability,sensitivity and integration degree,and enhance flexibility of system design.

MIXED-GRAINED CMOS FIELD PROGRAMMABLE ANALOG ARRAY FOR SMART SENSORY APPLICATIONS

The drive towards shorter design cycles for analog integrated circuits has given impetus to the development of Field Programmable Analog Arrays(FPAAs),which are the analogue counterparts of Field Programmable Gate Arrays(FPGAs).In this paper,we present a new design methodology which using FPAA as a powerful analog front-end processing platform in the smart sensory microsystem.The proposed FPAA contains 16 homogeneous mixed-grained Configurable Analog Blocks(CABs) which house a variety of processing elements especially the proposed fine-grained Core Configurable Amplifiers(CCAs).The high flexible CABs allow the FPAA operating in both continuous-time and discrete-time approaches suitable to support variety of sensors.To reduce the nonideal parasitic effects and save area,the fat-tree interconnection network is adopted in this FPAA.The functionality of this FPAA is demonstrated through embedding of voltage and capacitive sensor signal readout circuits and a configurable band pass filter.The minimal detectable voltage and capacitor achieves 38 uV and 8.3 aF respectively within 100 Hz sensor bandwidth.The power consumption comparison of CCA in three applications shows that the FPAA has high power efficiency.And the simulation results also show that the FPAA has good tolerance with wide PVT variations.

Design of PLC control system of RTG spreader in Qingdao Port Container Terminal

The control method of rubber tyre gantry （RTG） spreader in Qingdao Port Container Terminal is logic board control,which has many shortcomings such as expensive spare parts and high faults.This paper designs a new control system using programmable logic controller （PLC） centralized control to replace the original logic board control.The new system mainly contains complete ELME spreader control scheme design,hardware selection and PLC control program development.Its field application shows that the system has characteristics of high efficiency,low running cost,easy maintenance.

Design of ispPAC-based Humidity Sensor Signal Processing Circuits

The widely used sensitive elements of humidity sensors can be divided into 3 types,i.e.,resistor,capacitor,and electrolyte.Humidity sensors consisting of these sensitive elements have corresponding signal processing circuit unique to each type of sensitive elements.This paper presents an ispPAC (in-system programmable Programmable Analog Circuit) -based humidity sensor signal processing circuit designed with software method and implemented with in-system programmable simulators.Practical operation shows that humidity sensor signal processing circuits of this kind,exhibit stable and reliable performance.

High-Bandwidth,Low-Power CMOS Transistor Based CAB for Field Programmable Analog Array

This article presents an integrated current mode configurable analog block(CAB)system for field-programmable analog array(FPAA).The proposed architecture is based on the complementary metal-oxide semiconductor(CMOS)transistor level design where MOSFET transistors operating in the saturation region are adopted.The proposed CAB architecture is designed to implement six of thewidely used current mode operations in analog processing systems:addition,subtraction,integration,multiplication,division,and pass operation.The functionality of the proposed CAB is demonstrated through these six operations,where each operation is chosen based on the user’s selection in the CAB interface system.The architecture of the CAB system proposes an optimized way of designing and integrating only three functional cells with the interface circuitry to achieve the six operations.Furthermore,optimized programming and digital tuning circuitry are implemented in the architecture to control and interface with the functional cells.Moreover,these designed programming and tuning circuitries play an essential role in optimizing the performance of the proposed design.Simulation of the proposed CMOS Transistor Based CAB system is carried out using Tanner EDA Tools in 0.35μm standard CMOS technology.The design uses a±1.5 V power supply and results in maximum 3 dB bandwidth of 34.9 MHz and an approximate size of 0.0537 mm2.This demonstrates the advantages of the design over the current state-of-the-art designs presented for comparison in this article.Consequently,the proposed design has a clear aspect of simplicity,low power consumption,and high bandwidth operation,which makes it a suitable candidate for mobile telecommunications applications.

A NEW APPROACH TO PROGRAMMABLE LOGIC ARRAY FOR SINGLE-CLOCK CMOS

Programmable Logic Array (PLA) is an important building circuit of VLSI chips and some of the FPGA architectures have evolved from the basic PLA architectures. In this letter, a dynamic and static mixed PLA with single-phased clock is presented. Combining both dynamic and static design style rather than introducing additional interface-buffers overcomes the racing problem, thereby saves the chip area. Besides inheriting the advantages of dynamic circuit-low power dissipation and compact structure, this approach also provides high-speed operation.

Precise,programmable biological circuits

Several new components for biological circuits have been developed by researchers,These components are key building blocks for constructing precisely functioning and programmable bio-computers."The ability to combine biological components at will in a modular,plug-and-play fashion means that we now approach the stage when the concept of programming as we know it from software engineering can be applied to

Application of FPGA in Process Tomography Systems

This paper will provide some insights on the application of Field Programmable Gate Array (FPGA) in process tomography. The focus of this paper will be to investigate the performance of the technology with respect to various tomography systems and comparison to other similar technologies including the Application Specific Integrated Circuit (ASIC), Graphics Processing Unit (GPU) and the microcontroller. Fundamentally, the FPGA is primarily used in the Data Acquisition System (DAQ) due to its better performance and better trade-off as compared to competitor technologies. However, the drawback of using FPGA is that it is relatively more expensive.

Design and implementation of high speed TDI CCD timing-driven circuits

The time delay integration charge coupled device(TDI CCD)is the key component in remote sensing systems.The paper analyzes the structure and the working principles of the device according to a customized TDI CCD chip.Employing the special clock resources and large-scale phase locked logic(PLL)in field-programmable gate arrays(FPGA),a timing-driven approach is proposed,using which all timing signals including reset gate,horizontal and vertical timing signals,are implemented in one chip.This not only reduces printed circuit board(PCB)space,but also enhances the portability of the system.By studying and calculating CCD parameters thoroughly,load capacity and power consumption,package,etc,are compared between various candidates chips,and detailed comparison results are also listed in table.Experimental results show that clock generator and driving circuit satisfy the requirements of high speed TDI CCD.

基于CC-Link/LT总线技术的低压供配电监控系统设计

在对低压配电系统研究的基础上,分析了现有系统存在的不足,提出了基于CC-Link/LT总线技术的低压配电监控系统解决方案,实现了对低压供配电设备监视、控制和管理,达到了提高系统可靠性、可控性和快速响应的目的。文中对基于CC-Link/LT总线的低压配电监控系统的硬件组成、网络拓扑进行了较详尽的介绍,并结合实际操作经验,设定了若干系统控制规则,给出了系统各控制部分的程序框图。

基于Intel 8254的运动平台数/模转换电路设计

提出了一种新型的运动平台数/模转换(D/A)电路。利用可编程定时/计数器8254具有可编程单次脉冲、对主频进行分频等特点,设计了一种数/模转换电路。实际应用表明,这种数/模转换电路简单实用,工作稳定,且成本低、抗干扰能力较强、实时性好,已经成功地应用于某型飞行模拟器三自由度运动平台控制系统中。该电路还可推广应用于飞行模拟器的仪表控制系统、操纵负荷仿真系统的数/模转换电路中。

Low-loss chip-scale programmable silicon photonic processor

Chip-scale programmable optical signal processors are often used to flexibly manipulate the optical signals for satisfying the demands in various applications,such as lidar,radar,and artificial intelligence.Silicon photonics has unique advantages of ultra-high integration density as well as CMOS compatibility,and thus makes it possible to develop large-scale programmable optical signal processors.The challenge is the high silicon waveguides propagation losses and the high calibration complexity for all tuning elements due to the random phase errors.In this paper,we propose and demonstrate a programmable silicon photonic processor for the first time by introducing low-loss multimode photonic waveguide spirals and low-random-phase-error Mach-Zehnder switches.The present chip-scale programmable silicon photonic processor comprises a 1×4 variable power splitter based on cascaded Mach-Zehnder couplers(MZCs),four Ge/Si photodetectors,four channels of thermally-tunable optical delaylines.Each channel consists of a continuously-tuning phase shifter based on a waveguide spiral with a micro-heater and a digitally-tuning delayline realized with cascaded waveguide-spiral delaylines and MZSs for 5.68 ps time-delay step.Particularly,these waveguide spirals used here are designed to be as wide as 2μm,enabling an ultralow propagation loss of 0.28 dB/cm.Meanwhile,these MZCs and MZSs are designed with 2-μm-wide arm waveguides,and thus the random phase errors in the MZC/MZS arms are negligible,in which case the calibration for these MZSs/MZCs becomes easy and furthermore the power consumption for compensating the phase errors can be reduced greatly.Finally,this programmable silicon photonic processor is demonstrated successfully to verify a number of distinctively different functionalities,including tunable time-delay,microwave photonic beamforming,arbitrary optical signal filtering,and arbitrary waveform generation.

Principle and architecture of parallel reconfiguration circuit for ternary optical computer

Reconfiguration is the key to produce an applicable ternary optical computer （TOC）. The method to implement the reconfiguration function determines whether a TOC can step into applied fields or not. In this work, a design of the reconfiguration circuit based on field programmable gates array （FPGA） is proposed, and the structure of the entire hardware system is discussed.

Aptix System ExplorerTM使用方法初探

本文描述了AptixSystemExplorerTM硬件仿真系统两种工作方式 (MVP&Incir cuit)的基本原理及流程 ,分析了该系统的特点 ,并给出了如何利用其中的InCircuit模式实现对In tel 82 74芯片的测试 。

A routing algorithm for FPGAs with time-multiplexed interconnects

Previous studies show that interconnects occupy a large portion of the timing budget and area in FPGAs.In this work,we propose a time-multiplexing technique on FPGA interconnects.In order to fully exploit this interconnect architecture,we propose a time-multiplexed routing algorithm that can actively identify qualified nets and schedule them to multiplexable wires.We validate the algorithm by using the router to implement 20 benchmark circuits to time-multiplexed FPGAs.We achieve a 38%smaller minimum channel width and 3.8%smaller circuit critical path delay compared with the state-of-the-art architecture router when a wire can be time-multiplexed six times in a cycle.

基于FPGA和LabWindows的音频DAC测试方案开发与实现

电子设备集成度的提高对于音频集成电路生产和测试等环节的要求越来越高,尤其是音频数模转换器(Digital to Analog Converter,DAC),本质上为数模混合信号电路,采用数模混合信号自动化测试设备(Automatic Test Equipment,ATE)价格昂贵,而采用传统自动测试仪测试覆盖率低、测试时间长,导致这类电路的测试成本较高且测试产能不足。介绍了一种基于现场可编程门阵列(Field Programmable Gate Array,FPGA)和LabWindows的音频DAC电路测试方案,硬件上用FPGA实现音频测试所需的直接数字频率合成(Direct Digital Frequency Synthesizers,DDFS)模块,软件上通过运用LabWindows自带的采样、加窗、快速傅里叶变换(Fast Fourier Transform,FFT)等数字信号处理函数,快速准确地测试各项模拟参数,并在用户界面(User Interface,UI)显示测试值和后台保存测试数据。

Design and Implementation of Single Chip WCDMA High Speed Channel Decoder

A memory and driving clock efficient design scheme to achieve WCDMA high-speed channel decoder on a single XILINX’ XVC1000E FPGA chip is presented. Using a modified MAP algorithm, say parallel Sliding Window logarithmic Maximum A Posterior (PSW-log-MAP), the on-chip turbo decoder can decode an information bit by only an average of two clocks per iteration. On the other hand, a high-parallel pipeline Viterbi algorithm is adopted to realize the 256-state convolutional code decoding. The final decoder with an 8×chip-clock (30 72MHz) driving can concurrently process a data rate up to 2 5Mbps of turbo coded sequences and a data rate over 400kbps of convolutional codes. There is no extern memory needed. Test results show that the decoding performance is only 0 2～0 3dB or less lost comparing to float simulation.

一种双三次插值实时超分辨率VLSI设计

视频超分辨率技术具有广阔的应用前景,但基于深度学习方法的算法复杂度过高,难以实现实时计算.因此,近年来研究者们开始探索基于现场可编程逻辑门阵列(Field Programmable Gate Array,FPGA)的超分辨率算法加速器,以利用FPGA的优势来提高算法的性能和能耗,实现实时的视频超分辨率.设计了一种基于FPGA的高效高速双三次线性插值超大规模集成电路(Very Large Scale Integration Circuit,VLSI)架构,可用于4倍实时视频超分辨率.该FPGA架构解决了实现双三次插值过程中所需的复杂内存访问模式的问题,并提出了一种基于乒乓操作的数据重排硬件设计,将算法输出的特定顺序数据重新以行为主进行排列,使得硬件能够直接或较为简单地对接HDMI等视频接口.此外,采用状态机、流水线等方式降低设计功耗和减少时序违例,使得整个硬件设计可以更高频率运行.本研究在Zynq-7020 FPGA上实现了硬件架构,能够实时将qHD(960×540)的视频超采样为UHD(3840×2160)高清视频.实验结果表明,该硬件设计只需缓存1行图像像素,延迟仅为9.6μs,帧率达到192.9 Hz,成功实现实时处理.游戏图像数据集的测试结果表明,该设计峰值信噪比最高可达35.67 dB,结构相似度达到96.3%.

用于多气象传感器的模拟前端集成电路设计

设计了一款适用于多气象传感器的模拟前端集成电路,主要包含LDO、可编程增益放大器、SAR ADC以及湿度测量电路。可编程增益放大器采用全差分轨对轨运放作为主体结构来抑制噪声,同时采用连续时间Auto-Zero校准技术来降低其输入失调电压。对于14位SAR ADC,为降低DAC电容阵列的平均功耗和面积,设计了基于V_(CM)-based开关切换策略的分段式差分DAC电容阵列。最后基于湿度传感器电容值与矩形波频率之间关系的原理,设计了湿度测量电路,湿度测量电路频率误差为0.03%。该模拟前端电路基于华虹0.18μm CMOS工艺,并通过Cadence Spectre软件进行电路设计、版图绘制以及仿真验证。后仿真结果表明,电路整体可以实现从输入模拟信号的放大,到最终输出数字码的功能,其有效数(ENOB)为11.40 bit,SINAD为70.37 dB,SNR为71.05 dB,SFDR为83.85 dBc,THD为-78.55 dB。