Proposal for sequential Stern-Gerlach experiment with programmable quantum processors

The historical significance of the Stern–Gerlach(SG)experiment lies in its provision of the initial evidence for space quantization.Over time,its sequential form has evolved into an elegant paradigm that effectively illustrates the fundamental principles of quantum theory.To date,the practical implementation of the sequential SG experiment has not been fully achieved.In this study,we demonstrate the capability of programmable quantum processors to simulate the sequential SG experiment.The specific parametric shallow quantum circuits,which are suitable for the limitations of current noisy quantum hardware,are given to replicate the functionality of SG devices with the ability to perform measurements in different directions.Surprisingly,it has been demonstrated that Wigner’s SG interferometer can be readily implemented in our sequential quantum circuit.With the utilization of the identical circuits,it is also feasible to implement Wheeler’s delayed-choice experiment.We propose the utilization of cross-shaped programmable quantum processors to showcase sequential experiments,and the simulation results demonstrate a strong alignment with theoretical predictions.With the rapid advancement of cloud-based quantum computing,such as BAQIS Quafu,it is our belief that the proposed solution is well-suited for deployment on the cloud,allowing for public accessibility.Our findings not only expand the potential applications of quantum computers,but also contribute to a deeper comprehension of the fundamental principles underlying quantum theory.

Efficient cache replacement framework based on access hotness for spacecraft processors

A notable portion of cachelines in real-world workloads exhibits inner non-uniform access behaviors.However,modern cache management rarely considers this fine-grained feature,which impacts the effective cache capacity of contemporary high-performance spacecraft processors.To harness these non-uniform access behaviors,an efficient cache replacement framework featuring an auxiliary cache specifically designed to retain evicted hot data was proposed.This framework reconstructs the cache replacement policy,facilitating data migration between the main cache and the auxiliary cache.Unlike traditional cacheline-granularity policies,the approach excels at identifying and evicting infrequently used data,thereby optimizing cache utilization.The evaluation shows impressive performance improvement,especially on workloads with irregular access patterns.Benefiting from fine granularity,the proposal achieves superior storage efficiency compared with commonly used cache management schemes,providing a potential optimization opportunity for modern resource-constrained processors,such as spacecraft processors.Furthermore,the framework complements existing modern cache replacement policies and can be seamlessly integrated with minimal modifications,enhancing their overall efficacy.

Speeding up the MATLAB complex networks package using graphic processors

The availability of computers and communication networks allows us to gather and analyse data on a far larger scale than previously. At present, it is believed that statistics is a suitable method to analyse networks with millions, or more, of vertices. The MATLAB language, with its mass of statistical functions, is a good choice to rapidly realize an algorithm prototype of complex networks. The performance of the MATLAB codes can be further improved by using graphic processor units （GPU）. This paper presents the strategies and performance of the GPU implementation of a complex networks package, and the Jacket toolbox of MATLAB is used. Compared with some commercially available CPU implementations, GPU can achieve a speedup of, on average, 11.3x. The experimental result proves that the GPU platform combined with the MATLAB language is a good combination for complex network research.

SDN-Based Switch Implementation on Network Processors

Virtualization is the key technology of cloud computing. Network virtualization plays an important role in this field. Its performance is very relevant to network virtualizing. Nowadays its implementations are mainly based on the idea of Software Define Network (SDN). Open vSwitch is a sort of software virtual switch, which conforms to the OpenFlow protocol standard. It is basically deployed in the Linux kernel hypervisor. This leads to its performance relatively poor because of the limited system resource. In turn, the packet process throughput is very low.In this paper, we present a Cavium-based Open vSwitch implementation. The Cavium platform features with multi cores and couples of hard ac-celerators. It supports zero-copy of packets and handles packet more quickly. We also carry some experiments on the platform. It indicates that we can use it in the enterprise network or campus network as convergence layer and core layer device.

LOGIC STRUCTURE OF PROGRAMMABLE INSTRUCTIONS FOR JAVA PROCESSORS

There are varieties of embedded systems in the world. It is a big challenge to optimize the instruction sets of System on Chips (SoCs) according to different systems' working environments. The idea of programmable instruction set is an effective method to gain embedded system's re-configurability. This letter presents a logic module for Java processor to be capable of using programmable instruction set. Cost (area, power, and timing) of the module is trivial. Such module is also reusable for other embedded system solutions besides Java systems.

Multi-core optimization for conjugate gradient benchmark on heterogeneous processors

Developing parallel applications on heterogeneous processors is facing the challenges of 'memory wall',due to limited capacity of local storage,limited bandwidth and long latency for memory access. Aiming at this problem,a parallelization approach was proposed with six memory optimization schemes for CG,four schemes of them aiming at all kinds of sparse matrix-vector multiplication (SPMV) operation. Conducted on IBM QS20,the parallelization approach can reach up to 21 and 133 times speedups with size A and B,respectively,compared with single power processor element. Finally,the conclusion is drawn that the peak bandwidth of memory access on Cell BE can be obtained in SPMV,simple computation is more efficient on heterogeneous processors and loop-unrolling can hide local storage access latency while executing scalar operation on SIMD cores.

High-Level Portable Programming Language for Optimized Memory Use of Network Processors

Network processors (NPs) are widely used for programmable and high-performance networks;however, the programs for NPs are less portable, the number of NP program developers is small, and the development cost is high. To solve these problems, this paper proposes an open, high-level, and portable programming language called “Phonepl”, which is independent from vendor-specific proprietary hardware and software but can be translated into an NP program with high performance especially in the memory use. A common NP hardware feature is that a whole packet is stored in DRAM, but the header is cached in SRAM. Phonepl has a hardware-independent abstraction of this feature so that it allows programmers mostly unconscious of this hardware feature. To implement the abstraction, four representations of packet data type that cover all the packet operations (including substring, concatenation, input, and output) are introduced. Phonepl have been implemented on Octeon NPs used in plug-ins for a network-virtualization environment called the VNode Infrastructure, and several packet-handling programs were evaluated. As for the evaluation result, the conversion throughput is close to the wire rate, i.e., 10 Gbps, and no packet loss (by cache miss) occurs when the packet size is 256 bytes or larger.

Trends of Communication Processors

Processors have been playing important roles in both communication infrastructure systems and terminals.In this paper,both application specific and general purpose processors for communications are discussed including the roles,the history,the current situations,and the trends.One trend is that ASIPs(Application Specific Instruction-set Processors) are taking over ASICs(Application Specific Integrated Circuits) because of the increasing needs both on performance and compatibility of multi-modes.The trend opened opportunities for researchers crossing the boundary between communications and computer architecture.Another trend is the serverlization,i.e.,more infrastructure equipments are replaced by servers.The trend opened opportunities for researchers working towards high performance computing for communication,such as research on communication algorithm kernels and real time programming methods on servers.

Dynamic Power Dissipation Control Method for Real-Time Processors Based on Hardware Multithreading

In order to eliminate the energy waste caused by the traditional static hardware multithreaded processor used in real-time embedded system working in the low workload situation, the energy efficiency of the hardware multithread is discussed and a novel dynamic multithreaded architecture is proposed. The proposed architecture saves the energy wasted by removing idle threads without manipulation on the original architecture, fulfills a seamless switching mechanism which protects active threads and avoids pipeline stall during power mode switching. The report of an implemented dynamic multithreaded processor with 45 nm process from synthesis tool indicates that the area of dynamic multithreaded architecture is only 2.27% higher than the static one in achieving dynamic power dissipation, and consumes 1.3% more power in the same peak performance.

Processors处理器

2003年里，我们在处理器市场上看到了一幕幕重头戏的上演,基于Hyper Threading技术的Pentium4处理器、Pentium 4 EE、AMD Athlon 64、AMD Athlon 64FX系列，这些新产品的快速推出让人有目不暇接的感觉。

基于双DSP(Digital Signal Processor)结构的有源滤波器检测及控制系统

简要介绍了DigitalSignalProcessor(DSP)的发展及其性能特点 ,详细讨论了一种利用双DSP构成的有源滤波器检测及控制系统的实现和基本结构及算法 .

一种用于Multi-Processor测量系统的NOC结构的路由节点设计及性能评估

本文提出了一种用于多处理器(Multi-Processor)测量系统的NOC结构的路由节点的微结构,并详细描述了路由节点的各个部分结构及其各自功能。为了说明本文提出的结构的可行性和实用性,本文设计了一套以DSP和FPGA为基础的用于NOC结构仿真的硬件平台,评估了路由节点的资源消耗。最后,本文通过16个路由节点建立了一个基于4×4Mesh拓扑结构的NOC。通过仿真,得到了该网络在不同通信模式下的不同注入率情况下的延时、吞吐率、和面积消耗等性能,并与采用输出缓冲的路由节点进行了比较。同时,针对VOQ(virtual output queue)和输出缓冲大小这两个影响网络性能的重要微结构参数,给出了比较和分析结果。

A SMART COMPENSATION SYSTEM BASED ON MCA7707 PROCESSOR

This paper presents a smart compensation system based on MCA7707 (a kind of signal processor). The li near errors and high order errors of a sensor (especially piezoresistive sensor) can be corrected by using this system. It can optimize the process of piezoresi stive sensor calibration and compensation, then, a total error factor within 0.2 % of the sensor′s repeatability errors is obtained. Data are recorded and coeff icients are determined automatically by this system, thus, the sensor compensati on is simplified greatly. For operating easily, a wizard compensation program is designed to correct every error and to get the optimum compensation.

A VLIW Architecture Stream Cryptographic Processor for Information Security

As an important branch of information security algorithms,the efficient and flexible implementation of stream ciphers is vital.Existing implementation methods,such as FPGA,GPP and ASIC,provide a good support,but they could not achieve a better tradeoff between high speed processing and high flexibility.ASIC has fast processing speed,but its flexibility is poor,GPP has high flexibility,but the processing speed is slow,FPGA has high flexibility and processing speed,but the resource utilization is very low.This paper studies a stream cryptographic processor which can efficiently and flexibly implement a variety of stream cipher algorithms.By analyzing the structure model,processing characteristics and storage characteristics of stream ciphers,a reconfigurable stream cryptographic processor with special instructions based on VLIW is presented,which has separate/cluster storage structure and is oriented to stream cipher operations.The proposed instruction structure can effectively support stream cipher processing with multiple data bit widths,parallelism among stream cipher processing with different data bit widths,and parallelism among branch control and stream cipher processing with high instruction level parallelism;the designed separate/clustered special bit registers and general register heaps,key register heaps can satisfy cryptographic requirements.So the proposed processor not only flexibly accomplishes the combination of multiple basic stream cipher operations to finish stream cipher algorithms.It has been implemented with 0.18μm CMOS technology,the test results show that the frequency can reach 200 MHz,and power consumption is 310 mw.Ten kinds of stream ciphers were realized in the processor.The key stream generation throughput of Grain-80,W7,MICKEY,ACHTERBAHN and Shrink algorithm is 100 Mbps,66.67 Mbps,66.67 Mbps,50 Mbps and 800 Mbps,respectively.The test result shows that the processor presented can achieve good tradeoff between high performance and flexibility of stream ciphers.

The history of Cochlear^(TM) Nucleus~ sound processor upgrades:30 years and counting

Objective:To review developments in sound processors over the past 30 years that have resulted in significant improvements in outcomes for Nucleus~ recipients.

Performance assessment of a spiral methanol to hydrogen fuel processor for fuel cell applications

A novel design of plate-type microchannel reactor has been developed for fuel cell-grade hydrogen production.Commercial Cu/Zn/Al2O3 was used as catalyst for the reforming reaction,and its effectiveness was evaluated on the mole fraction of products,methanol conversion,hydrogen yield and the amount of carbon monoxide under various operating conditions.Subsequently,0.5 wt% Ru/Al2O3 as methanation catalyst was prepared by impregnation method and coupled with MSR step to evaluate the capability of methanol processor for CO reduction.Based on the experimental results,the optimum conditions were obtained as feed flow rate of 5mL/h and temperature of 250℃,leading to a low CO selectivity and high H2 yield.The designed reformer with catalyst coated layer was compared with the conventional packed bed reformer at the same operating conditions.The constructed fuel processor had a good performance and excellent capability for on-board hydrogen production.

A distributed cross-domain register filefor reconfigurable cryptographic processor

Due to the fact that the register files seriously affect the performance and area of coarse-grained reconfigurable cryptographic processors, an efficient structure of the distributed cross-domain register file is proposed to realize a cryptographic processor with a high performance and a lowarea cost. In order to meet the demands of high performance and high flexibility at a lowarea cost, a union structure with the multi-ports access structure, i, e., a distributed crossdomain register file, is designed by analyzing the algorithm features of different ciphers. Considering different algorithm requirements of the global register files and local register files,the circuit design is realized by adopting different design parameters under TSMC( Taiwan Semiconductor Manufacturing Company) 40 nm CMOS( complementary metal oxide semiconductor) technology and compared with other similar works. The experimental results showthat the proposed distributed cross-domain register structure can effectively improve the performance of the unit area, of which the total performance of block per cycle is improved by17. 79% and performance of block per cycle per area is improved by 117%.

Ultra-Fast Next Generation Human Genome Sequencing Data Processing Using DRAGEN^TMBio-IT Processor for Precision Medicine

Slow speed of the Next-Generation sequencing data analysis, compared to the latest high throughput sequencers such as HiSeq X system, using the current industry standard genome analysis pipeline, has been the major factor of data backlog which limits the real-time use of genomic data for precision medicine. This study demonstrates the DRAGEN Bio-IT Processor as a potential candidate to remove the “Big Data Bottleneck”. DRAGENTM accomplished the variant calling, for ~40× coverage WGS data in as low as ~30 minutes using a single command, achieving the over 50-fold data analysis speed while maintaining the similar or better variant calling accuracy than the standard GATK Best Practices workflow. This systematic comparison provides the faster and efficient NGS data analysis alternative to NGS-based healthcare industries and research institutes to meet the requirement for precision medicine based healthcare.