A new approach of incremental placement approach is described.The obtained timing information drives an efficient net-based placement technique,which dynamically adapts the net weights during successive placement step...A new approach of incremental placement approach is described.The obtained timing information drives an efficient net-based placement technique,which dynamically adapts the net weights during successive placement steps.Several methods to combine timing optimization and congestion reducing together are proposed.Cells on critical paths are replaced according to timing and congestion constraints.Experimental results show that our approach can efficiently reduce cycle time and enhance route ability.The max path delay is reduced by 10% on an average afterincremental placement on wirelength-optimized circuits.And it achieves the same quality with a high speed up compared to timing driven detailed placement algorithm.展开更多
A new incremental placement algorithm C-ECOP for standard cell layout is presented to reduce routing congestion.It first estimates the routing congestion through a new routing model.Then,it formulates an integer linea...A new incremental placement algorithm C-ECOP for standard cell layout is presented to reduce routing congestion.It first estimates the routing congestion through a new routing model.Then,it formulates an integer linear programming (ILP) problem to determine cell flow direction and to avoid the conflictions between adjacent congestion areas.Experimental results show that the algorithm can considerably reduce routing congestion and preserve the performance of the initial placement with high speed.展开更多
A new algorithm W ECOP is presented to effect incremental changes on a standard cell layout automatically.This algorithm deals with cell inserting and cell moving based on rows instead of on cells as most placement a...A new algorithm W ECOP is presented to effect incremental changes on a standard cell layout automatically.This algorithm deals with cell inserting and cell moving based on rows instead of on cells as most placement algorithms usually do.An integer programming problem is formulated to minimize the adjustment on the initial placement and a heuristic method is presented to search for a shifting path so as to optimize the wirelength.Test of W ECOP on a group of practical test cases shows that the algorithm can successfully accomplish incremental placement with good quality and high speed.展开更多
Power is the major challenge threatening the progress of very large scale integration （VLSI） technology development. In ultra-deep submicron VLSI designs, clock network size must be minimized to reduce power consump...Power is the major challenge threatening the progress of very large scale integration （VLSI） technology development. In ultra-deep submicron VLSI designs, clock network size must be minimized to reduce power consumption, power supply noise, and the number of clock buffers which are vulnerable to process variations. Traditional design methodologies usually let the clock router independently undertake the clock network minimization. Since clock routing is based on register locations, register placement actually strongly influences the clock network size. This paper describes a clock network design methodology that optimizes register placement. For a given cell placement result, incremental modifications are performed based on the clock skew specifications by moving registers toward preferred locations that may reduce the clock network size. At the same time, the side-effects to logic cell placement, such as signal net wirelength and critical path delay, are controlled. Test results on benchmark circuits show that the methodology can considerably reduce clock network size with limited impact on signal net wirelength and critical path delay.展开更多
A new clock-driven ECO placement algorithm is pr es ented for standard-cell layout design based on the table-lookup delay model.It considers useful clock skew information in the placement stage.It also modifies the ...A new clock-driven ECO placement algorithm is pr es ented for standard-cell layout design based on the table-lookup delay model.It considers useful clock skew information in the placement stage.It also modifies the positions of cells locally to make better preparation for the clock routing . Experimental results show that with little influence to other circuit performa nce,the algorithm can improve permissible skew range distribution evidently.展开更多
文摘A new approach of incremental placement approach is described.The obtained timing information drives an efficient net-based placement technique,which dynamically adapts the net weights during successive placement steps.Several methods to combine timing optimization and congestion reducing together are proposed.Cells on critical paths are replaced according to timing and congestion constraints.Experimental results show that our approach can efficiently reduce cycle time and enhance route ability.The max path delay is reduced by 10% on an average afterincremental placement on wirelength-optimized circuits.And it achieves the same quality with a high speed up compared to timing driven detailed placement algorithm.
文摘A new incremental placement algorithm C-ECOP for standard cell layout is presented to reduce routing congestion.It first estimates the routing congestion through a new routing model.Then,it formulates an integer linear programming (ILP) problem to determine cell flow direction and to avoid the conflictions between adjacent congestion areas.Experimental results show that the algorithm can considerably reduce routing congestion and preserve the performance of the initial placement with high speed.
文摘A new algorithm W ECOP is presented to effect incremental changes on a standard cell layout automatically.This algorithm deals with cell inserting and cell moving based on rows instead of on cells as most placement algorithms usually do.An integer programming problem is formulated to minimize the adjustment on the initial placement and a heuristic method is presented to search for a shifting path so as to optimize the wirelength.Test of W ECOP on a group of practical test cases shows that the algorithm can successfully accomplish incremental placement with good quality and high speed.
基金the National Natural Science Foundation of China (No. 60776026)
文摘Power is the major challenge threatening the progress of very large scale integration （VLSI） technology development. In ultra-deep submicron VLSI designs, clock network size must be minimized to reduce power consumption, power supply noise, and the number of clock buffers which are vulnerable to process variations. Traditional design methodologies usually let the clock router independently undertake the clock network minimization. Since clock routing is based on register locations, register placement actually strongly influences the clock network size. This paper describes a clock network design methodology that optimizes register placement. For a given cell placement result, incremental modifications are performed based on the clock skew specifications by moving registers toward preferred locations that may reduce the clock network size. At the same time, the side-effects to logic cell placement, such as signal net wirelength and critical path delay, are controlled. Test results on benchmark circuits show that the methodology can considerably reduce clock network size with limited impact on signal net wirelength and critical path delay.
文摘A new clock-driven ECO placement algorithm is pr es ented for standard-cell layout design based on the table-lookup delay model.It considers useful clock skew information in the placement stage.It also modifies the positions of cells locally to make better preparation for the clock routing . Experimental results show that with little influence to other circuit performa nce,the algorithm can improve permissible skew range distribution evidently.
