Based on an avalanche photodiode（ APD） detecting array working in Geiger mode（ GM-APD）, a high-performance infrared sensor readout integrated circuit（ ROIC） used for infrared 3D（ three-dimensional） imaging is ...Based on an avalanche photodiode（ APD） detecting array working in Geiger mode（ GM-APD）, a high-performance infrared sensor readout integrated circuit（ ROIC） used for infrared 3D（ three-dimensional） imaging is proposed. The system mainly consists of three functional modules, including active quenching circuit（ AQC）, time-to-digital converter（ TDC） circuit and other timing controller circuit. Each AQC and TDC circuit together constitutes the pixel circuit. Under the cooperation with other modules, the current signal generated by the GM-APD sensor is detected by the AQC, and the photon time-of-flight（ TOF） is measured and converted to a digital signal output to achieve a better noise suppression and a higher detection sensitivity by the TDC. The ROIC circuit is fabricated by the CSMC 0. 5 μm standard CMOS technology. The array size is 8 × 8, and the center distance of two adjacent cells is 100μm. The measurement results of the chip showthat the performance of the circuit is good, and the chip can achieve 1 ns time resolution with a 250 MHz reference clock, and the circuit can be used in the array structure of the infrared detection system or focal plane array（ FPA）.展开更多
The diode infrared focal plane array uses the silicon diodes as a sensitive device for infrared signal measurement. By the infrared radiation, the infrared focal plane can produces small voltage signals. For the tradi...The diode infrared focal plane array uses the silicon diodes as a sensitive device for infrared signal measurement. By the infrared radiation, the infrared focal plane can produces small voltage signals. For the traditional readout circuit structures are designed to process current signals, they cannot be applied to it. In this paper, a new readout circuit for the diode un-cooled infrared focal plane array is developed. The principle of detector array signal readout and small signal amplification is given in detail. The readout circuit is designed and simulated by using the Central Semiconductor Manufacturing Corporation （CSMC） 0.5 μm complementary metal-oxide-semiconductor transistor （CMOS） technology library. Cadence Spectre simulation results show that the scheme can be applied to the CMOS readout integrated circuit （ROIC） with a larger array, such as 320×240 size array.展开更多
After approximately half a century of development, HgCdTe infrared detectors have become the first choice for high performance infrared detectors, which are widely used in various industry sectors, including military ...After approximately half a century of development, HgCdTe infrared detectors have become the first choice for high performance infrared detectors, which are widely used in various industry sectors, including military tracking, military reconnaissance, infrared guidance, infrared warning, weather forecasting, and resource detection. Further development in infrared applications requires future HgCdTe infrared detectors to exhibit features such as larger focal plane array format and thus higher imaging resolution. An effective approach to develop HgCdTe infrared detectors with a larger array format size is to develop the small pixel technology. In this article, we present a review on the developmental history and current status of small pixel technology for HgCdTe infrared detectors, as well as the main challenges and potential solutions in developing this technology. It is predicted that the pixel size of long-wave HgCdTe infrared detectors can be reduced to5 μm, while that of mid-wave HgCdTe infrared detectors can be reduced to 3 μm. Although significant progress has been made in this area, the development of small pixel technology for HgCdTe infrared detectors still faces significant challenges such as flip-chip bonding, interconnection, and charge processing capacity of readout circuits. Various approaches have been proposed to address these challenges, including three-dimensional stacking integration and readout circuits based on microelectromechanical systems.展开更多
基金The Natural Science Foundation of Jiangsu Province(No.BK2012559)Qing Lan Project of Jiangsu Province
文摘Based on an avalanche photodiode（ APD） detecting array working in Geiger mode（ GM-APD）, a high-performance infrared sensor readout integrated circuit（ ROIC） used for infrared 3D（ three-dimensional） imaging is proposed. The system mainly consists of three functional modules, including active quenching circuit（ AQC）, time-to-digital converter（ TDC） circuit and other timing controller circuit. Each AQC and TDC circuit together constitutes the pixel circuit. Under the cooperation with other modules, the current signal generated by the GM-APD sensor is detected by the AQC, and the photon time-of-flight（ TOF） is measured and converted to a digital signal output to achieve a better noise suppression and a higher detection sensitivity by the TDC. The ROIC circuit is fabricated by the CSMC 0. 5 μm standard CMOS technology. The array size is 8 × 8, and the center distance of two adjacent cells is 100μm. The measurement results of the chip showthat the performance of the circuit is good, and the chip can achieve 1 ns time resolution with a 250 MHz reference clock, and the circuit can be used in the array structure of the infrared detection system or focal plane array（ FPA）.
基金supported by the Fundamental Research Funds for the Central Universities under Grant No. 2009JBM001
文摘The diode infrared focal plane array uses the silicon diodes as a sensitive device for infrared signal measurement. By the infrared radiation, the infrared focal plane can produces small voltage signals. For the traditional readout circuit structures are designed to process current signals, they cannot be applied to it. In this paper, a new readout circuit for the diode un-cooled infrared focal plane array is developed. The principle of detector array signal readout and small signal amplification is given in detail. The readout circuit is designed and simulated by using the Central Semiconductor Manufacturing Corporation （CSMC） 0.5 μm complementary metal-oxide-semiconductor transistor （CMOS） technology library. Cadence Spectre simulation results show that the scheme can be applied to the CMOS readout integrated circuit （ROIC） with a larger array, such as 320×240 size array.
文摘After approximately half a century of development, HgCdTe infrared detectors have become the first choice for high performance infrared detectors, which are widely used in various industry sectors, including military tracking, military reconnaissance, infrared guidance, infrared warning, weather forecasting, and resource detection. Further development in infrared applications requires future HgCdTe infrared detectors to exhibit features such as larger focal plane array format and thus higher imaging resolution. An effective approach to develop HgCdTe infrared detectors with a larger array format size is to develop the small pixel technology. In this article, we present a review on the developmental history and current status of small pixel technology for HgCdTe infrared detectors, as well as the main challenges and potential solutions in developing this technology. It is predicted that the pixel size of long-wave HgCdTe infrared detectors can be reduced to5 μm, while that of mid-wave HgCdTe infrared detectors can be reduced to 3 μm. Although significant progress has been made in this area, the development of small pixel technology for HgCdTe infrared detectors still faces significant challenges such as flip-chip bonding, interconnection, and charge processing capacity of readout circuits. Various approaches have been proposed to address these challenges, including three-dimensional stacking integration and readout circuits based on microelectromechanical systems.
