Novel lateral insulated gate bipolar transistor on SOI substrate for optimizing hot-carrier degradation

A novel lateral insulated gate bipolar transistor on a silicon-on-insulator substrate SOI-LIGBT with a special low-doped P-well structure is proposed.The P-well structure is added to attach the P-body under the channel so as to reduce the linear anode current degradation without additional process.The influence of the length and depth of the P-well on the hot-carrier HC reliability of the SOI-LIGBT is studied.With the increase in the length of the P-well the perpendicular electric field peak and the impact ionization peak diminish resulting in the reduction of the hot-carrier degradation. In addition the impact ionization will be weakened with the increase in the depth of the P-well which also makes the hot-carrier degradation decrease.Considering the effect of the low-doped P-well and the process windows the length and depth of the P-well are both chosen as 2 μm.

SiC gate-controlled bipolar field effect composite transistor with polysilicon region for improving on-state current

A novel silicon carbide gate-controlled bipolar field effect composite transistor with poly silicon region(SiC GCBTP)is proposed.Different from the traditional electrode connection mode of SiC vertical diffused MOS(VDMOS),the P+region of P-well is connected with the gate in SiC GCBTP,and the polysilicon region is added between the P+region and the gate.By this method,additional minority carriers can be injected into the drift region at on-state,and the distribution of minority carriers in the drift region will be optimized,so the on-state current is increased.In terms of static characteristics,it has the same high breakdown voltage(811 V)as SiC VDMOS whose length of drift is 5.5μm.The on-state current of SiC GCBTP is 2.47×10^(-3)A/μm(V_(G)=10 V,V_(D)=10 V)which is 5.7 times of that of SiC IGBT and 36.4 times of that of SiC VDMOS.In terms of dynamic characteristics,the turn-on time of SiC GCBTP is only 0.425 ns.And the turn-off time of SiC GCBTP is similar to that of SIC insulated gate bipolar transistor(IGBT),which is 114.72 ns.

A dual-gate and dielectric-inserted lateral trench insulated gate bipolar transistor on a silicon-on-insulator substrate

In this paper, a novel dual-gate and dielectric-inserted lateral trench insulated gate bipolar transistor （DGDI LTIGBT） structure, which features a double extended trench gate and a dielectric inserted in the drift region, is proposed and discussed. The device can not only decrease the specific on-resistance Ron,sp , but also simultaneously improve the temperature performance. Simulation results show that the proposed LTIGBT achieves an ultra-low on-state voltage drop of 1.31 V at 700 A·cm-2 with a small half-cell pitch of 10.5 μm, a specific on-resistance R on,sp of 187 mΩ·mm2, and a high breakdown voltage of 250 V. The on-state voltage drop of the DGDI LTIGBT is 18% less than that of the DI LTIGBT and 30.3% less than that of the conventional LTIGBT. The proposed LTIGBT exhibits a good positive temperature coefficient for safety paralleling to handling larger currents and enhances the short-circuit capability while maintaining a low self-heating effect. Furthermore, it also shows a better tradeoff between the specific on-resistance and the turnoff loss, although it has a longer turnoff delay time.

Insulated gate bipolar transistor inverter for arc welding

This paper introduces the Insulated gate bipolar transistor(IGBT)in- verter for arc welding.The principle of the inverter,the structure and charac- teristics of IGBT and the current feedback system using LEM current transduc- er are discussed.By the measurement of its efficiency and power factor and the tests of welding processes,the developed 150A IGBT inverter proves to be a kind of energy-saving portable power supply for arc welding with broad prospects.

A high voltage silicon-on-insulator lateral insulated gate bipolar transistor with a reduced cell-pitch

A high voltage（〉 600 V） integrable silicon-on-insulator（SOI） trench-type lateral insulated gate bipolar transistor（LIGBT） with a reduced cell-pitch is proposed.The LIGBT features multiple trenches（MTs）：two oxide trenches in the drift region and a trench gate extended to the buried oxide（BOX）.Firstly,the oxide trenches enhance electric field strength because of the lower permittivity of oxide than that of Si.Secondly,oxide trenches bring in multi-directional depletion,leading to a reshaped electric field distribution and an enhanced reduced-surface electric-field（RESURF） effect.Both increase the breakdown voltage（BV）.Thirdly,oxide trenches fold the drift region around the oxide trenches,leading to a reduced cell-pitch.Finally,the oxide trenches enhance the conductivity modulation,resulting in a high electron/hole concentration in the drift region as well as a low forward voltage drop（Von）.The oxide trenches cause a low anode-cathode capacitance,which increases the switching speed and reduces the turn-off energy loss（Eoff）.The MT SOI LIGBT exhibits a BV of 603 V at a small cell-pitch of 24 μm,a Von of 1.03 V at 100 A/cm-2,a turn-off time of 250 ns and Eoff of 4.1×10？3 mJ.The trench gate extended to BOX synchronously acts as dielectric isolation between high voltage LIGBT and low voltage circuits,simplifying the fabrication processes.

Improving dynamic characteristics for IGBTs by using interleaved trench gate

A novel trench insulated gate bipolar transistor(IGBT) with improved dynamic characteristics is proposed and investigated. The poly gate and poly emitter of the proposed IGBT are arranged alternately along the trench. A self-biased p-MOSFET is formed on the emitter side. Owing to this unique three-dimensional(3D) trench architecture, both the turnoff characteristic and the turn-on characteristic can be greatly improved. At the turn-off moment, the maximum electric field and impact ionization rate of the proposed IGBT decrease and the dynamic avalanche(DA) is suppressed. Comparing with the carrier-stored trench gate bipolar transistor(CSTBT), the turn-off loss(E_(off)) of the proposed IGBT also decreases by 31% at the same ON-state voltage. At the turn-on moment, the built-in p-MOSFET reduces the reverse displacement current(I_(G_dis)), which is conducive to lowing dI_(C)/d_(t). As a result, compared with the CSTBT with the same turn-on loss(E_(on)), at I_(C) = 20 A/cm^(2), the proposed IGBT decreases by 35% of collector surge current(I_(surge)) and 52% of dI_(C)/d_(t).

Heat dissipation enhancement method for finned heat sink for AGV motor driver's IGBT module

With the widespread use of high-power and highly integrated insulated gate bipolar transistor(IGBT),their cooling methods have become challenging.This paper proposes a liquid cooling scheme for heavy-duty automated guided vehicle(AGV)motor driver in port environment,and improves heat dissipation by analyzing and optimizing the core component of finned heat sink.Firstly,the temperature distribution of the initial scheme is studied by using Fluent software,and the heat transfer characteristics of the finned heat sink are obtained through numerical analysis.Secondly,an orthogonal test is designed and combined with the response surface methodology to optimize the structural parameters of the finned heat sink,resulting in a 14.57%increase in the heat dissipation effect.Finally,the effectiveness of heat dissipation enhancement is verified.This work provides valuable insights into improving the heat dissipation of IGBT modules and heat sinks,and provides guidance for their future applications.

Ultralow turnoff loss dual-gate SOI LIGBT with trench gate barrier and carrier stored layer

A novel ultralow turnoff loss dual-gate silicon-on-insulator （SOI） lateral insulated gate bipolar transistor （LIGBT） is proposed. The proposed SOI LIGBT features an extra trench gate inserted between the p-well and n-drift, and an n-type carrier stored （CS） layer beneath the p-well. In the on-state, the extra trench gate acts as a barrier, which increases the cartier density at the cathode side of n-drift region, resulting in a decrease of the on-state voltage drop （Von）. In the off-state, due to the uniform carder distribution and the assisted depletion effect induced by the extra trench gate, large number of carriers can be removed at the initial turnoff process, contributing to a low turnoff loss （Eoff）. Moreover, owing to the dual-gate field plates and CS layer, the carrier density beneath the p-well can greatly increase, which further improves the tradeoff between Eoff and Von. Simulation results show that Eoff of the proposed SOI LIGBT can decrease by 77% compared with the conventional trench gate SOI LIGBT at the same Von of 1.1 V.

A 4H-SiC trench IGBT with controllable hole-extracting path for low loss

A novel 4H-Si C trench insulated gate bipolar transistor(IGBT)with a controllable hole-extracting(CHE)path is proposed and investigated in this paper.The CHE path is controlled by metal semiconductor gate(MES gate)and metal oxide semiconductor gate(MOS gate)in the p-shield region.The grounded p-shield region can significantly suppress the high electric field around gate oxide in Si C devices,but it weakens the conductivity modulation in the Si C trench IGBT by rapidly sweeping out holes.This effect can be eliminated by introducing the CHE path.The CHE path is pinched off by the high gate bias voltage at on-state to maintain high conductivity modulation and obtain a comparatively low on-state voltage(VON).During the turn-off transient,the CHE path is formed,which contributes to a decreased turn-off loss(EOFF).Based on numerical simulation,the EOFFof the proposed IGBT is reduced by 89%compared with the conventional IGBT at the same VONand the VONof the proposed IGBT is reduced by 50%compared to the grounded p-shield IGBT at the same EOFF.In addition,the average power reduction for the proposed device can be 51.0%to 81.7%and 58.2%to 72.1%with its counterparts at a wide frequency range of 500 Hz to 10 k Hz,revealing a great improvement of frequency characteristics.

Trench gate GaN IGBT with controlled hole injection efficiency

In this paper,a novel trench gate gallium nitride(GaN)insulated gate bipolar transistor(GaN IGBT),in which the collector is divided into multiple regions to control the hole injection efficiency,is designed and theoretically studied.The incorporation of a P+/P-multi-region alternating structure in the collector region mitigates hole injection within the collector region.When the device is in forward conduction,the conductivity modulation effect results in a reduced storage of carriers in the drift region.As a result,the number of carriers requiring extraction during device turn-off is minimized,leading to a faster turn-off speed.The results illustrate that the GaN IGBT with controlled hole injection efficiency(CEH GaN IGBT)exhibits markedly enhanced performance compared to conventional GaN IGBT,showing a remarkable 42.2%reduction in turn-off time and a notable 28.5%decrease in turn-off loss.

A novel high performance TFS SJ IGBT with a buried oxide layer

A novel high performance trench field stop （TFS） superjunction （S J） insulated gate bipolar transistor （IGBT） with a buried oxide （BO） layer is proposed in this paper. The BO layer inserted between the P-base and the SJ drift region acts as a barrier layer for the hole-carrier in the drift region. Therefore, conduction modulation in the emitter side of the SJ drift region is enhanced significantly and the carrier distribution in the drift region is optimized for the proposed structure. As a result, compared with the conventional TFS SJ IGBT （Conv-SJ）, the proposed BO-SJ IGBT structure possesses a drastically reduced on-state voltage drop （gce（on）） and an improved tradeoff between gee（on） and turn-off loss （Eoff）, with no breakdown voltage （BV） degraded. The results show that with the spacing between the gate and the BO layer Wo = 0.2 μm, the thickness of the BO layer Lo = 0.2 μm, the thickness of the drift region Ld = 90 μm, the half width and doping concentration of the N- and P-pillars Wn = Wp = 2.5μm and Nn = Np = 3 × 10^15 cm^-3, the Vce（on） and Eoff of the proposed structure are 1.08 V and 2.81 mJ/cm2 with the collector doping concentration Nc = 1 × 10^18 cm^-3 and 1.12 V and 1.73 mJ/cm2 with Nc = 5 × 10^17 cm^-3, respectively. However, with the same device parameters, the Vce（on） and Eoff for the Conv-SJ are 1.81 V and 2.88 mJ/cm2 with Nc= 1 × 10^18 cm^-3 and 1.98 V and 2.82 mJ/cm2 with Nc = 5 ×10^17 cm^-3, respectively. Meanwhile, the BV of the proposed structure and Conv-SJ are 1414 V and 1413 V, respectively.

Study on Rotor IGBT Chopper Control for Induction Motor Drive

Rotor chopper control is a simple and effective drive method for induction motor. This paper presents a novel IGBT chopper topology,which can both adjust rotor resistance and protect IGBT efficiently. Investigation on the quasi transient state of the rotor rectifying circuit is made, and a nonlinear mapping between the equivalent resistance and the duty cycle is deduced. Furthermore, the method for determining the magnitude of the external resistor is introduced.

Superjunction nanoscale partially narrow mesa IGBT towards superior performance

We present a detailed study of a superjunction （S J） nanoscale partially narrow mesa （PNM） insulated gate bipolar transistor （IGBT） structure. This structure is created by combining the nanoscale PNM structure and the SJ structure together. It demonstrates an ultra-low saturation voltage （Vce（sat）） and low turn-off loss （Eoff） while maintaining other device parameters. Compared with the conventional 1.2 kV trench IGBT, our simulation result shows that the gce（sat） of this structure decreases to 0.94 V, which is close to the theoretical limit of 1.2 kV IGBT, Meanwhile, the fall time decreases from 109.7 ns to 12 ns and the Eoff is down to only 37% of that of the conventional structure. The superior tradeoff characteristic between Vce（sat） and Eoff is presented owing to the nanometer level mesa width and SJ structure. Moreover, the short circuit degeneration phenomenon in the very narrow mesa structure due to the collector-induced barriers lowering （CIBL） effect is not observed in this structure. Thus, enough short circuit ability can be achieved by using wide, floating P-well technique. Based on these structure advantages, the SJ-PNM-IGBT with nanoscale mesa width indicates a potentially superior overall performance towards the IGBT parameter limit.

Fast-switching SOI-LIGBT with compound dielectric buried layer and assistant-depletion trench

A lateral insulated gate bipolar transistor(LIGBT)based on silicon-on-insulator(SOI)structure is proposed and investigated.This device features a compound dielectric buried layer(CDBL)and an assistant-depletion trench(ADT).The CDBL is employed to introduce two high electric field peaks that optimize the electric field distributions and that,under the same breakdown voltage(BV)condition,allow the CDBL to acquire a drift region of shorter length and a smaller number of stored carriers.Reducing their numbers helps in fast-switching.Furthermore,the ADT contributes to the rapid extraction of the stored carriers from the drift region as well as the formation of an additional heat-flow channel.The simulation results show that the BV of the proposed LIGBT is increased by 113%compared with the conventional SOI LIGBT of the same length L_(D).Contrastingly,the length of the drift region of the proposed device(11.2μm)is about one third that of a traditional device(33μm)with the same BV of 141 V.Therefore,the turn-off loss(E_(OFF))of the CDBL SOI LIGBT is decreased by 88.7%compared with a conventional SOI LIGBT when the forward voltage drop(VF)is 1.64 V.Moreover,the short-circuit failure time of the proposed device is 45%longer than that of the conventional SOI LIGBT.Therefor,the proposed CDBL SOI LIGBT exhibits a better V_(F)-E_(OFF)tradeoff and an improved short-circuit robustness.

Plug-in Gate-loop Compensators for Series-connected IGBT Drivers in a Solid-state Fault Current Limiter

A solid-state fault current limiter(SSFCL)is the key protective equipment in a direct current distribution network.In order to meet the high voltage requirements and reduce costs,implementing a SSFCL based on series-connected insulated gate bipolar transistors(IGBTs)is a promising approach.However,voltage unbalancing of IGBTs would be introduced if the gateloops of the IGBTs are non-identical.In this paper,a plug-in gate-loop compensator with discrete gate voltage feedback and pulsewidth current compensation is proposed.The main merits are:1)with the plug-in structure,the extra current sources only provide small power to fine-tune the gate-loop without affecting the functions provided by the commercial IGBT gate driver;2)the gate-emitter voltages of IGBTs are compared with the preset thresholds to obtain control criterion,and the pulsewidths of the current sources are controlled for gate-loop compensation,thus both analog-digital and digital-analog converters are avoided;3)the control law is easy to implement in FPGA,and is robust to voltage variation of power-loops.With the proposed compensator,the voltage unbalancing is alleviated immediately at the present switching cycle,and further eliminated cycle-by-cycle during the current limitation process.Experimental results verify the feasibility of the proposed compensator.

Press-pack IGBTs for HVDC and FACTS

The popularity of insulated gate bipolar transistors(IGBTs)for use in high-voltage direct current(HVDC)transmission and flexible AC transmission systems(FACTS)is increasing.Unfortunately,for these applications wire-bond IGBT technology has a number of shortcomings,such as insufficient current ratings for the most powerful schemes,and inability to fail to short-circuit.Press-pack IGBT technology,conversely,offers increased current ratings,and an inherent short-circuit failure mode,making it a more attractive choice for HVDC and FACTS.However,the design and manufacture of these devices requires a comprehensive understanding of the unique technical challenges,which differ markedly from those for wirebond modules or traditional pressure contact devices.Specific challenges include providing a high degree of mechanical protection for the IGBT chip against normal operating stresses.Furthermore,it is essential to achieve uniform contact pressure across each chip surface to ensure optimum performance.To achieve this,manufacturers have designed products that use rigid copper electrodes manufactured to tighter tolerances than for other pressure contact devices,such as thyristors,and products that use compliant electrodes,incorporating spring assemblies.Dynex is in the advanced stages of development of press-pack IGBT technology with demonstrated robust solutions for the technical challenges outlined in this paper.Design success has been achieved through the use of state-of-the-art simulations in conjunction with a long history of manufacturing expertise for bipolar and IGBT products.Finally,multiple press-pack IGBT variants are currently undergoing evaluation tests prior to product release.

Transient performance and intelligent combination control of a novel spray cooling loop system

Effective thermal control systems are essential for the reliable working of insulated gate bipolar transistors （IGBTs） in many applications. A novel spray cooling loop system with integrated sintered porous copper wick （SCLS-SPC） is proposed to meet the requirements of higher device level heat fluxes and the harsh environments in some applications such as hybrid, fuel cell vehicles and aerospace. Fuzzy logic and proportional-integral-derivative （PID） policies are applied to adjust the electronic temperature within a safe working range. To evaluate the thermal control effect, a mathematical model of a 4-node thermal network and pump are established for predicting the dynamics of the SCLS-SPC. Moreover, the transient response of the 4 nodes and vapor mass flowrate under no control, PID and Fuzzy-PID are numerically investigated and discussed in detail.

Overview of power electronics technology and applications in power generation, transmission and distribution

The main objective of this paper is three-fold.First, to provide an overview of the current status of the power electronics technology, one of the key actors in the upcoming smart grid paradigm enabling maximum power throughputs and near-instantaneous control of voltages and currents in all links of the power system chain. Second, to provide a bridge between the power systems and the power electronic communities, in terms of their differing appreciation of how these devices perform when connected to the power grid. Third, to discuss on the role that the power electronics technology will play in supporting the aims and objectives of future decarbonized power systems. This paper merges the equipment, control techniques and methods used in flexible alternating current transmission systems(FACTS) and high voltage direct transmission(HVDC) equipment to enable a single, coherent approach to address a specific power system problem, using ‘best of breed’ solutions bearing in mind technical, economic and environmental issues.

Theoretical calculation of the p-emitter length for snapback-free reverse-conducting IGBT

A physically based equation for predicting required p-emitter length of a snapback-free reverse- conducting insulated gate bipolar transistor （RC-IGBT） with field-stop structure is proposed. The n-buffer resis- tances above the p-emitter region with anode geometries of linear strip, circular and annular type are calculated, and based on this, the minimum p-emitter lengths of those three geometries are given and verified by simulation. It is found that good agreement was achieved between the numerical calculation and simulation results. Moreover, the calculation results show that the annular case needs the shortest p-emitter length for RC-IGBT to be snapback-free.

Application of artificial neural network for switching loss modeling in power IGBTs

The modeling of switching loss in semiconductor power devices is important in practice for the prediction and evaluation of thermal safety and system reliability.Both simulation-based behavioral models and data processing-based empirical models are difficult and have limited applications.Although the artificial neural network(ANN) algorithm has often been used for modeling, it has never been used for modeling insulated gate bipolar transistor(IGBT) transient loss.In this paper, we attempt to use the ANN method for this purpose, using a customized switching loss test bench.We compare its performance with two conventional curve-fitting models and verify the results by experiment.Our model is generally superior in calculation speed, accuracy, and data requirement, and is also able to be extended to loss modeling for all kinds of semiconductor power devices.