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Pixelated non-volatile programmable photonic integrated circuits with 20-level intermediate states 被引量:1
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作者 Wenyu Chen Shiyuan Liu Jinlong Zhu 《International Journal of Extreme Manufacturing》 SCIE EI CAS CSCD 2024年第3期477-487,共11页
Multi-level programmable photonic integrated circuits(PICs)and optical metasurfaces have gained widespread attention in many fields,such as neuromorphic photonics,opticalcommunications,and quantum information.In this ... Multi-level programmable photonic integrated circuits(PICs)and optical metasurfaces have gained widespread attention in many fields,such as neuromorphic photonics,opticalcommunications,and quantum information.In this paper,we propose pixelated programmable Si_(3)N_(4)PICs with record-high 20-level intermediate states at 785 nm wavelength.Such flexibility in phase or amplitude modulation is achieved by a programmable Sb_(2)S_(3)matrix,the footprint of whose elements can be as small as 1.2μm,limited only by the optical diffraction limit of anin-house developed pulsed laser writing system.We believe our work lays the foundation for laser-writing ultra-high-level(20 levels and even more)programmable photonic systems and metasurfaces based on phase change materials,which could catalyze diverse applications such as programmable neuromorphic photonics,biosensing,optical computing,photonic quantum computing,and reconfigurable metasurfaces. 展开更多
关键词 programmable photonic integrated circuits phase change materials multi-level intermediate states metasurfaces
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Carbon nanotube integrated circuit technology:purification,assembly and integration
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作者 Jianlei Cui Fengqi Wei Xuesong Mei 《International Journal of Extreme Manufacturing》 SCIE EI CAS CSCD 2024年第3期120-138,共19页
As the manufacturing process of silicon-based integrated circuits(ICs)approaches its physical limit,the quantum effect of silicon-based field-effect transistors(FETs)has become increasingly evident.And the burgeoning ... As the manufacturing process of silicon-based integrated circuits(ICs)approaches its physical limit,the quantum effect of silicon-based field-effect transistors(FETs)has become increasingly evident.And the burgeoning carbon-based semiconductor technology has become one of the most disruptive technologies in the post-Moore era.As one-dimensional nanomaterials,carbon nanotubes(CNTs)are far superior to silicon at the same technology nodes of FETs because of their excellent electrical transport and scaling properties,rendering them the most competitive material in the next-generation ICs technology.However,certain challenges impede the industrialization of CNTs,particularly in terms of material preparation,which significantly hinders the development of CNT-based ICs.Focusing on CNT-based ICs technology,this review summarizes its main technical status,development trends,existing challenges,and future development directions. 展开更多
关键词 carbon nanotubes integrated circuits field-effect transistors post-Moore
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A Thermal-Conscious Integrated Circuit Power Model and Its Impact on Dynamic Voltage Scaling Techniques 被引量:2
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作者 刘勇攀 杨华中 汪蕙 《Journal of Semiconductors》 EI CAS CSCD 北大核心 2007年第4期530-536,共7页
We propose a novel thermal-conscious power model for integrated circuits that can accurately predict power and temperature under voltage scaling. Experimental results show that the leakage power consumption is underes... We propose a novel thermal-conscious power model for integrated circuits that can accurately predict power and temperature under voltage scaling. Experimental results show that the leakage power consumption is underestimated by 52 % if thermal effects are omitted. Furthermore, an inconsistency arises when energy and temperature are simultaneously optimized by dynamic voltage scaling. Temperature is a limiting factor for future integrated circuits,and the thermal optimization approach can attain a temperature reduction of up to 12℃ with less than 1.8% energy penalty compared with the energy optimization one. 展开更多
关键词 CMOS integrated circuits power model TEMPERATURE DVS
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适用于SiC MOSFET的漏源电压积分自适应快速短路保护电路研究 被引量:1
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作者 李虹 胡肖飞 +1 位作者 王玉婷 曾洋斌 《中国电机工程学报》 EI CSCD 北大核心 2024年第4期1542-1552,I0024,共12页
SiC MOSFET因其高击穿电压、高开关速度、低导通损耗等性能优势而被广泛应用于各类电力电子变换器中。然而,由于其短路耐受时间仅为2~7μs,且随母线电压升高而缩短,快速可靠的短路保护电路已成为其推广应用的关键技术之一。为应对不同... SiC MOSFET因其高击穿电压、高开关速度、低导通损耗等性能优势而被广泛应用于各类电力电子变换器中。然而,由于其短路耐受时间仅为2~7μs,且随母线电压升高而缩短,快速可靠的短路保护电路已成为其推广应用的关键技术之一。为应对不同母线电压下的Si C MOSFET短路故障,文中提出一种基于漏源电压积分的自适应快速短路保护方法(drain-sourcevoltageintegration-basedadaptivefast short-circuit protection method,DSVI-AFSCPM),研究所提出的DSVI-AFSCPM在硬开关短路(hardswitchingfault,HSF)和负载短路(fault under load,FUL)条件下的保护性能,进而研究不同母线电压对DSVI-AFSCPM的作用机理。同时,探究Si CMOSFET工作温度对其响应速度的影响。最后,搭建实验平台,对所提出的DSVI-AFSCPM在发生硬开关短路和负载短路时不同母线电压、不同工作温度下的保护性能进行实验测试。实验结果表明,所提出的DSVI-AFSCPM在不同母线电压下具有良好的保护速度自适应性,即母线电压越高,短路保护速度越快,并且其响应速度受Si CMOSFET工作温度影响较小,两种短路工况下工作温度从25℃变化到125℃,短路保护时间变化不超过90 ns。因此,该文为Si CMOSFET在不同母线电压下的可靠使用提供一定技术支撑。 展开更多
关键词 碳化硅金属氧化物半导体场效应晶体管 短路保护 漏源电压积分 母线电压 自适应
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超低介电常数的多孔F-pSiCOH薄膜制备及其紫外固化处理
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作者 陈云 《化工新型材料》 CAS CSCD 北大核心 2024年第S01期128-131,142,共5页
面向高性能集成电路可靠性设计要求之下,开展以硅集成电路(IC)三维集成器件超低介电常数的介电薄膜研究。采用化学气相沉积法制备了一种超低介电常数(k)值的多孔F-pSiCOH薄膜。利用傅里叶变换红外光谱测定了多孔F-pSiCOH薄膜的化学结构... 面向高性能集成电路可靠性设计要求之下,开展以硅集成电路(IC)三维集成器件超低介电常数的介电薄膜研究。采用化学气相沉积法制备了一种超低介电常数(k)值的多孔F-pSiCOH薄膜。利用傅里叶变换红外光谱测定了多孔F-pSiCOH薄膜的化学结构和化学键,并探究了紫外线辐射对多孔F-pSiCOH薄膜机械性能的影响。结果表明:纳米孔和氟原子的引入能有效地降低介电常数,使多孔F-SiCOH薄膜的k值为2.15。紫外固化处理增强了多孔F-pSiCOH薄膜的弹性模量,使多孔F-pSiCOH薄膜的弹性模量从4.84GPa增大到5.76GPa,力学性能得到优化。 展开更多
关键词 硅集成电路 低介电常数介电材料 多孔SicOH薄膜 紫外固化
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Emerging MoS_(2)Wafer-Scale Technique for Integrated Circuits 被引量:5
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作者 Zimeng Ye Chao Tan +4 位作者 Xiaolei Huang Yi Ouyang Lei Yang Zegao Wang Mingdong Dong 《Nano-Micro Letters》 SCIE EI CAS CSCD 2023年第3期129-170,共42页
As an outstanding representative of layered materials,molybdenum disulfide(MoS_(2))has excellent physical properties,such as high carrier mobility,stability,and abundance on earth.Moreover,its reasonable band gap and ... As an outstanding representative of layered materials,molybdenum disulfide(MoS_(2))has excellent physical properties,such as high carrier mobility,stability,and abundance on earth.Moreover,its reasonable band gap and microelectronic compatible fabrication characteristics makes it the most promising candidate in future advanced integrated circuits such as logical electronics,flexible electronics,and focal-plane photodetector.However,to realize the all-aspects application of MoS_(2),the research on obtaining high-quality and large-area films need to be continuously explored to promote its industrialization.Although the MoS_(2)grain size has already improved from several micrometers to sub-millimeters,the high-quality growth of wafer-scale MoS_(2)is still of great challenge.Herein,this review mainly focuses on the evolution of MoS_(2)by including chemical vapor deposition,metal–organic chemical vapor deposition,physical vapor deposition,and thermal conversion technology methods.The state-of-the-art research on the growth and optimization mechanism,including nucleation,orientation,grain,and defect engineering,is systematically summarized.Then,this review summarizes the wafer-scale application of MoS_(2)in a transistor,inverter,electronics,and photodetectors.Finally,the current challenges and future perspectives are outlined for the wafer-scale growth and application of MoS_(2). 展开更多
关键词 Wafer-scale growth Molybdenum disulfide Gas deposition integrated circuits
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X波段GaAs MMIC低噪声放大器设计研究
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作者 王国强 蒲颜 +2 位作者 万瑞捷 聂荣邹 朱海 《电声技术》 2024年第2期116-118,共3页
文章针对雷达和卫星通信等微波系统需求,设计一种X波段GaAs单片微波集成电路(Monolithic Microwave Integrated Circuit,MMIC)低噪声放大器。该电路为两级放大器级联结构,采用自偏置电路结构,实现单电源3.5 V供电。通过电感峰化和宽带... 文章针对雷达和卫星通信等微波系统需求,设计一种X波段GaAs单片微波集成电路(Monolithic Microwave Integrated Circuit,MMIC)低噪声放大器。该电路为两级放大器级联结构,采用自偏置电路结构,实现单电源3.5 V供电。通过电感峰化和宽带匹配等技术实现X波段的工作频率全覆盖,并实现较低的噪声系数。测试结果表明,在8~12 GHz频率范围内,低噪声放大器功率增益大于23 dB,噪声系数小于1.7 dB,输出1 dB压缩点功率大于13 dBm。 展开更多
关键词 低噪声放大器 X波段 单片微波集成电路(MMic)
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The Roadmap of 2D Materials and Devices Toward Chips 被引量:4
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作者 Anhan Liu Xiaowei Zhang +16 位作者 Ziyu Liu Yuning Li Xueyang Peng Xin Li Yue Qin Chen Hu Yanqing Qiu Han Jiang Yang Wang Yifan Li Jun Tang Jun Liu Hao Guo Tao Deng Songang Peng He Tian Tian‑Ling Ren 《Nano-Micro Letters》 SCIE EI CAS CSCD 2024年第6期343-438,共96页
Due to the constraints imposed by physical effects and performance degra certain limitations in sustaining the advancement of Moore’s law.Two-dimensional(2D)materials have emerged as highly promising candidates for t... Due to the constraints imposed by physical effects and performance degra certain limitations in sustaining the advancement of Moore’s law.Two-dimensional(2D)materials have emerged as highly promising candidates for the post-Moore era,offering significant potential in domains such as integrated circuits and next-generation computing.Here,in this review,the progress of 2D semiconductors in process engineering and various electronic applications are summarized.A careful introduction of material synthesis,transistor engineering focused on device configuration,dielectric engineering,contact engineering,and material integration are given first.Then 2D transistors for certain electronic applications including digital and analog circuits,heterogeneous integration chips,and sensing circuits are discussed.Moreover,several promising applications(artificial intelligence chips and quantum chips)based on specific mechanism devices are introduced.Finally,the challenges for 2D materials encountered in achieving circuit-level or system-level applications are analyzed,and potential development pathways or roadmaps are further speculated and outlooked. 展开更多
关键词 Two-dimensional materials ROADMAP integrated circuits Post-Moore era
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Test system of the front-end readout for an application-specific integrated circuit for the water Cherenkov detector array at the large high-altitude air shower observatory 被引量:5
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作者 Er-Lei Chen Lei Zhao +4 位作者 Li Yu Jia-Jun Qin Yu Liang Shu-Bin Liu Qi An 《Nuclear Science and Techniques》 SCIE CAS CSCD 2017年第6期140-149,共10页
The water Cherenkov detector array(WCDA) is an important part of the large high-altitude air shower observatory(LHAASO),which is in a research and development phase.The central scientific goal of LHAASO is to explore ... The water Cherenkov detector array(WCDA) is an important part of the large high-altitude air shower observatory(LHAASO),which is in a research and development phase.The central scientific goal of LHAASO is to explore the origin of high-energy cosmic rays of the universe and to push forward the frontier of new physics.To simplify the WCDA's readout electronics,a prototype of a front-end readout for an application-specific integrated circuit(ASIC) is designed based on the timeover-threshold method to achieve charge-to-time conversion.High-precision time measurement and charge measurement are necessary over a full dynamic range[1-4000photoelectrons(P.E.)].To evaluate the performance of this ASIC,a test system is designed that includes the front-end ASIC test module,digitization module,and test software.The first module needs to be customized for different ASIC versions,whereas the digitization module and test software are tested for general-purpose use.In the digitization module,a field programmable gate array-based time-todigital converter is designed with a bin size of 333 ps,which also integrates an inter-integrated circuit to configure the ASIC test module,and a universal serial bus interface is designed to transfer data to the remote computer.Test results indicate that the time resolution is better than 0.5 ns,and the charge resolution is better than 30%root mean square(RMS) at 1 P.E.and 3%RMS at 4000 P.E.,which are beyond the application requirements. 展开更多
关键词 Time and charge measurement PHOTOMULTIPLIER tube (PMT) Water CHERENKOV detector ARRAY Inter-integrated circuit Application-specific integrated circuit Test system
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Through-silicon-via crosstalk model and optimization design for three-dimensional integrated circuits 被引量:3
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作者 钱利波 朱樟明 +2 位作者 夏银水 丁瑞雪 杨银堂 《Chinese Physics B》 SCIE EI CAS CSCD 2014年第3期591-596,共6页
Through-silicon-via (TSV) to TSV crosstalk noise is one of the key factors affecting the signal integrity of three- dimensional integrated circuits (3D ICs). Based on the frequency dependent equivalent electrical ... Through-silicon-via (TSV) to TSV crosstalk noise is one of the key factors affecting the signal integrity of three- dimensional integrated circuits (3D ICs). Based on the frequency dependent equivalent electrical parameters for the TSV channel, an analytical crosstalk noise model is established to capture the TSV induced crosstalk noise. The impact of various design parameters including insulation dielectric, via pitch, via height, silicon conductivity, and terminal impedance on the crosstalk noise is analyzed with the proposed model. Two approaches are proposed to alleviate the TSV noise, namely, driver sizing and via shielding, and the SPICE results show 241 rnV and 379 mV reductions in the peak noise voltage, respectively. 展开更多
关键词 three-dimensional integrated circuits through-silicon-via crosstalk driver sizing via shielding
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High density Al2O3/TaN-based metal-insulatormetal capacitors in application to radio equency integrated circuits 被引量:3
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作者 丁士进 黄宇健 +3 位作者 黄玥 潘少辉 张卫 汪礼康 《Chinese Physics B》 SCIE EI CAS CSCD 2007年第9期2803-2808,共6页
Metal-insulator-metal (MIM) capacitors with atomic-layer-deposited Al2O3 dielectric and reactively sputtered TaN electrodes in application to radio frequency integrated circuits have been characterized electrically.... Metal-insulator-metal (MIM) capacitors with atomic-layer-deposited Al2O3 dielectric and reactively sputtered TaN electrodes in application to radio frequency integrated circuits have been characterized electrically. The capacitors exhibit a high density of about 6.05 fF/μm^2, a small leakage current of 4.8 × 10^-8 A/cm^2 at 3 V, a high breakdown electric field of 8.61 MV/cm as well as acceptable voltage coefficients of capacitance (VCCs) of 795 ppm/V2 and 268ppm/V at 1 MHz. The observed properties should be attributed to high-quality Al2O3 film and chemically stable TaN electrodes. Further, a logarithmically linear relationship between quadratic VCC and frequency is observed due to the change of relaxation time with carrier mobility in the dielectric. The conduction mechanism in the high field ranges is dominated by the Poole-Frenkel emission, and the leakage current in the low field ranges is likely to be associated with trap-assisted tunnelling. Meanwhile, the Al2O3 dielectric presents charge trapping under low voltage stresses, and defect generation under high voltage stresses, and it has a hard-breakdown performance. 展开更多
关键词 metal-insulator-metal atomic-layer-deposition AL2O3 radio frequency integrated circuit
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Hybrid material integration in silicon photonic integrated circuits 被引量:3
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作者 Swapnajit Chakravarty† Min Teng +1 位作者 Reza Safian Leimeng Zhuang 《Journal of Semiconductors》 EI CAS CSCD 2021年第4期33-42,共10页
Hybrid integration ofⅢ-Ⅴand ferroelectric materials is being broadly adopted to enhance functionalities in silicon photonic integrated circuits(PICs).Bonding and transfer printing have been the popular approaches fo... Hybrid integration ofⅢ-Ⅴand ferroelectric materials is being broadly adopted to enhance functionalities in silicon photonic integrated circuits(PICs).Bonding and transfer printing have been the popular approaches for integration of III–V gain media with silicon PICs.Similar approaches are also being considered for ferroelectrics to enable larger RF modulation bandwidths,higher linearity,lower optical loss integrated optical modulators on chip.In this paper,we review existing integration strategies ofⅢ-Ⅴmaterials and present a route towards hybrid integration of bothⅢ-Ⅴand ferroelectrics on the same chip.We show that adiabatic transformation of the optical mode between hybrid ferroelectric and silicon sections enables efficient transfer of optical modal energies for maximum overlap of the optical mode with the ferroelectric media,similar to approaches adopted to maximize optical overlap with the gain section,thereby reducing lasing thresholds for hybridⅢ-Ⅴintegration with silicon PICs.Preliminary designs are presented to enable a foundry compatible hybrid integration route of diverse functionalities on silicon PICs. 展开更多
关键词 CMOS technology photonic integrated circuits hybrid integration ferroelectric modulator
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High performance integrated photonic circuit based on inverse design method 被引量:6
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作者 Huixin Qi Zhuochen Du +3 位作者 Xiaoyong Hu Jiayu Yang Saisai Chu Qihuang Gong 《Opto-Electronic Advances》 SCIE EI CAS 2022年第10期22-34,共13页
The basic indexes of all-optical integrated photonic circuits include high-density integration,ultrafast response and ultralow energy consumption.Traditional methods mainly adopt conventional micro/nano-structures.The... The basic indexes of all-optical integrated photonic circuits include high-density integration,ultrafast response and ultralow energy consumption.Traditional methods mainly adopt conventional micro/nano-structures.The overall size of the circuit is large,usually reaches hundreds of microns.Besides,it is difficult to balance the ultrafast response and ultra-low energy consumption problem,and the crosstalk between two traditional devices is difficult to overcome.Here,we propose and experimentally demonstrate an approach based on inverse design method to realize a high-density,ultrafast and ultra-low energy consumption integrated photonic circuit with two all-optical switches controlling the input states of an all-optical XOR logic gate.The feature size of the whole circuit is only 2.5μm×7μm,and that of a single device is 2μm×2μm.The distance between two adjacent devices is as small as 1.5μm,within wavelength magnitude scale.Theoretical response time of the circuit is 150 fs,and the threshold energy is within 10 fJ/bit.We have also considered the crosstalk problem.The circuit also realizes a function of identifying two-digit logic signal results.Our work provides a new idea for the design of ultrafast,ultra-low energy consumption all-optical devices and the implementation of high-density photonic integrated circuits. 展开更多
关键词 all-optical integrated photonic circuit inverse design all-optical switch all-optical XOR logic gate
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4H-SiC CMOS高温集成电路设计与制造
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作者 陈浩炜 刘奥 +3 位作者 黄润华 杨勇 刘涛 柏松 《固体电子学研究与进展》 CAS 2024年第2期109-112,118,共5页
设计、制造并测试了基于碳化硅材料的横向MOSFET器件和CMOS电路。常温时,N型和P型MOSFET在片测试的阈值电压分别约为5.4 V和-6.3 V;温度达到300℃时,N型和P型MOSFET的阈值电压分别为4.3 V和-5.3 V。由N型和P型MOSFET组成的CMOS反相器在... 设计、制造并测试了基于碳化硅材料的横向MOSFET器件和CMOS电路。常温时,N型和P型MOSFET在片测试的阈值电压分别约为5.4 V和-6.3 V;温度达到300℃时,N型和P型MOSFET的阈值电压分别为4.3 V和-5.3 V。由N型和P型MOSFET组成的CMOS反相器在常温下输出的上升时间为1.44μs,下降时间为2.17μs,且在300℃高温条件下仍可正常工作。由CMOS反相器级联成的环形振荡器在常温下的测试工作频率为147 kHz,在高温下也可正常工作。 展开更多
关键词 碳化硅 CMOS 集成电路 反相器 环形振荡器
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Science Letters:The Moore’s Law for photonic integrated circuits 被引量:2
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作者 THYLEN L. HE Sailing +1 位作者 WOSINSKI L. DAI Daoxin 《Journal of Zhejiang University-Science A(Applied Physics & Engineering)》 SCIE EI CAS CSCD 2006年第12期1961-1967,共7页
We formulate a “Moore’s law” for photonic integrated circuits (PICs) and their spatial integration density using two methods. One is decomposing the integrated photonics devices of diverse types into equivalent bas... We formulate a “Moore’s law” for photonic integrated circuits (PICs) and their spatial integration density using two methods. One is decomposing the integrated photonics devices of diverse types into equivalent basic elements, which makes a comparison with the generic elements of electronic integrated circuits more meaningful. The other is making a complex compo- nent equivalent to a series of basic elements of the same functionality, which is used to calculate the integration density for func- tional components realized with different structures. The results serve as a benchmark of the evolution of PICs and we can con- clude that the density of integration measured in this way roughly increases by a factor of 2 per year. The prospects for a continued increase of spatial integration density are discussed. 展开更多
关键词 Moore's Law Photonic integrated circuit (Pic) Photonic lightwave circuit (PLC) Photonic integration density Photonic filters Photonic multiplexing
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A Full CMOS Integration Including ISFET Microsensors and Interface Circuit for Biochemical Applications 被引量:1
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作者 Jinbao Wei Haigang Yang +2 位作者 Hongguang Sun Zengjin Lin Shanhong Xia 《稀有金属材料与工程》 SCIE EI CAS CSCD 北大核心 2006年第A03期443-446,共4页
One of today's challenges is the integration of ISFETs in chemical and biochemical Microsystems.This article presents a full integration of ISFET chip containing the ISFET/REFET(reference FET) pair,ISFET/REFET amp... One of today's challenges is the integration of ISFETs in chemical and biochemical Microsystems.This article presents a full integration of ISFET chip containing the ISFET/REFET(reference FET) pair,ISFET/REFET amplifiers,bias current generator,as well as a reference electrode structure,all integrated on the same chip based on CMOS technology.The sensor chip was fabricated in a standard 0.35μm CMOS process(Chartered Semiconductor,Singapore).The extra post processing steps have been developed and added for depositing membranes.Finally,the pH response of the integrated sensor was measured with the interface circuit. 展开更多
关键词 ISFET interface circuit integration and post processing
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Reduction of signal reflection along through silicon via channel in high-speed three-dimensional integration circuit 被引量:1
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作者 刘晓贤 朱樟明 +2 位作者 杨银堂 王凤娟 丁瑞雪 《Chinese Physics B》 SCIE EI CAS CSCD 2014年第3期583-590,共8页
The through silicon via (TSV) technology has proven to be the critical enabler to realize a three-dimensional (3D) gigscale system with higher performance but shorter interconnect length. However, the received dig... The through silicon via (TSV) technology has proven to be the critical enabler to realize a three-dimensional (3D) gigscale system with higher performance but shorter interconnect length. However, the received digital signal after trans- mission through a TSV channel, composed of redistribution layers (RDLs), TSVs, and bumps, is degraded at a high data-rate due to the non-idealities of the channel. We propose the Chebyshev multisection transformers to reduce the signal reflec- tion of TSV channel when operating frequency goes up to 20 GHz, by which signal reflection coefficient ($11) and signal transmission coefficient ($21) are improved remarkably by 150% and 73.3%, respectively. Both the time delay and power dissipation are also reduced by 4% and 13.3%, respectively. The resistance-inductance-conductance-capacitance (RLGC) elements of the TSV channel are iterated from scattering (S)-parameters, and the proposed method of weakening the signal reflection is verified using high frequency simulator structure (HFSS) simulation software by Ansoft. 展开更多
关键词 three-dimensional integrated circuit through silicon via channel signal reflection S-PARAMETERS
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Human blood plasma-based electronic integrated circuit amplifier configuration 被引量:1
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作者 Shiv Prasad Kosta Manthan Manavadaria +4 位作者 Killol Pandya Yogesh.Prasad Kosta Shakti Kosta Harsh Mehta Jaimin Patel 《The Journal of Biomedical Research》 CAS 2013年第6期520-522,共3页
Dear Editor: There is accumulating evidence that human blood electronic circuit components and their application circuits become more and more important to cyborg implant/engineering, man-machine interface, hu- man ... Dear Editor: There is accumulating evidence that human blood electronic circuit components and their application circuits become more and more important to cyborg implant/engineering, man-machine interface, hu- man disease detection and healing, and artificial brain evolutionusl. Here, we report the first development of human plasma-based amplifier circuit in the dis- crete as well as integrated circuit (IC) configuration mode. Electrolytes in the human blood contain an enormous number of charge carriers such as positive and negative molecule/atom ions, which are electri- cally conducting media and therefore can be utilized for developing electronic circuit components and their application circuits. These electronic circuits obvi- ously have very high application impact potential towards bio-medical engineering and medical science and technology. 展开更多
关键词 ic MHz Human blood plasma-based electronic integrated circuit amplifier configuration CRO over
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Fabrication of integrated resistors in printed circuit boards 被引量:1
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作者 王守国 陈清远 《Journal of Central South University》 SCIE EI CAS 2011年第3期739-743,共5页
In order to utilize integrated passive technology in printed circuit boards (PCBs), manufacturing processing for integrated resistors by lamination method was investigated. Integrated resistors fabricated from Ohmeg... In order to utilize integrated passive technology in printed circuit boards (PCBs), manufacturing processing for integrated resistors by lamination method was investigated. Integrated resistors fabricated from Ohmega technologies in the experiment were 1 408 pieces per panel with four different patterns A, B, C and D and four resistance values of 25, 50, 75 and 100 fL Six panel per batch and four batches were performed totally. The testing was done for 960 pieces of integrated resistors randomly selected with the same size. The value distribution ranges and the relative standard deviation (RSD) show that the scatter degree of the resistance decreases with the resistor size increasing and/or with the resistance increasing. Patterns D with resistance of 75 and 100% for four patterns have the resistance value variances less than 10%. Patterns C and D with resistance of 100 Ω have the manufacturing tolerance less than 10%. The process capabilities are from about 0.6 to 1.6 for the designed testing patterns, which shows that the integrated resistors fabricated have the potential to be used in multilayer PCBs in the future. 展开更多
关键词 integrated resistors lamination method printed circuit boards integrated passive technology
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A 330-500 GHz Zero-Biased Broadband Tripler Based on Terahertz Monolithic Integrated Circuits 被引量:2
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作者 任田昊 张勇 +4 位作者 延波 徐锐敏 杨成樾 周静涛 金智 《Chinese Physics Letters》 SCIE CAS CSCD 2015年第2期31-34,共4页
A 330-500 GHz zero-biased broadband monolithic integrated tripler is reported. The measured results show that the maximum efficiency and the maximum output power are 2% and 194μW at 348 GHz. The saturation characteri... A 330-500 GHz zero-biased broadband monolithic integrated tripler is reported. The measured results show that the maximum efficiency and the maximum output power are 2% and 194μW at 348 GHz. The saturation characteristic test shows that the output i dB compression point is about -8.5 dBm at 334 GHz and the maximum efficiency is obtained at the point, which is slightly below the 1 dB compression point. Compared with the conventional hybrid integrated circuit, a major advantage of the monolithic integrated circuit is the significant improvement of reliability and consistency. In this work, a terahertz monolithic frequency multiplier at this band is designed and fabricated. 展开更多
关键词 InP InGaAs A 330-500 GHz Zero-Biased Broadband Tripler Based on Terahertz Monolithic integrated circuits dBm SBD
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