Large Eddy Simulation Study on the Turbulence and Flame Characteristics under Analogical Integral Scale and Turbulence Intensity of Turbulent Premixed Flames

Bunsen burner is a typical geometry for investigating the turbulence-flame interaction.In most experimental studies,only turbulence intensity u′and integral scale l0 are used to characterize the turbulent flow field,regardless of the perforation geometry of perforated plates.However,since the geometry influences the developing process and vortex broken,the plate geometry has to be considered when discussing the flame-turbulence interaction.In order to investigate conditions at the same l0 and u′using different geometries,large eddy simulation of CH_(4)/air flames with dynamic TF combustion model was performed.The model validation shows good agreement between Large Eddy Simulation(LES)and experimental results.In the non-reacting flows,the Vortex Stretching of circular-perforated plate condition is always larger than that of slot-perforated plate condition,which comes from the stresses in the flow fields to stretch the vorticity vector.In reacting flows,at the root of the flame,the Vortex Stretching plays a major role,and the total vorticity here of circular-perforated plate condition is still larger(53.8%and 300%larger than that of the slot-perforated plate at x/D=0 and x/D=2.5,respectively).More small-scale vortex in circular-perforated plate condition can affect and wrinkle the flame front to increase the Probability Density Function(PDF)at large curvatures.The 3D curvature distributions of both cases bias to negative values.The negative trend of curvatures at the instant flame front results from the Dilatation term.Also,the value of the Vortex Stretching and the Dilatation at the flame front of circular-perforated plate condition is obviously larger.

Two-phase micro-and macro-time scales in particle-laden turbulent channel flows

The micro- and macro-time scales in two-phase turbulent channel flows are investigated using the direct nu- merical simulation and the Lagrangian particle trajectory methods for the fluid- and the particle-phases, respectively. Lagrangian and Eulerian time scales of both phases are cal- culated using velocity correlation functions. Due to flow anisotropy, micro-time scales are not the same with the theo- retical estimations in large Reynolds number （isotropic） tur- bulence. Lagrangian macro-time scales of particle-phase and of fluid-phase seen by particles are both dependent on particle Stokes number. The fluid-phase Lagrangian inte- gral time scales increase with distance from the wall, longer than those time scales seen by particles. The Eulerian inte- gral macro-time scales increase in near-wall regions but de- crease in out-layer regions. The moving Eulerian time scales are also investigated and compared with Lagrangian integral time scales, and in good agreement with previous measure- ments and numerical predictions. For the fluid particles the micro Eulerian time scales are longer than the Lagrangian ones in the near wall regions, while away from the walls the micro Lagrangian time scales are longer. The Lagrangian integral time scales are longer than the Eulerian ones. The results are useful for further understanding two-phase flow physics and especially for constructing accurate prediction models of inertial particle dispersion.

CALL FOR PAPERS Dec.2018 Special Issue on Large Scale Renewable Energy Integration

Guest Editor in Chief:Professor Xiao-Ping Zhang, University of Birmingham The potential for renewable energy to make contributions to mitigating the impact of climate change is expected to increase significantly in the longer term. Renewable energy generation technologies including onshore wind, offshore wind, wave,tidal, marine current, and ocean thermal energy generation as well as PV power generation, which are considered

Novel Block Chain Technique for Data Privacy and Access Anonymity in Smart Healthcare

The Internet of Things (IoT) and Cloud computing are gaining popularity due to their numerous advantages, including the efficient utilization of internetand computing resources. In recent years, many more IoT applications have beenextensively used. For instance, Healthcare applications execute computations utilizing the user’s private data stored on cloud servers. However, the main obstaclesfaced by the extensive acceptance and usage of these emerging technologies aresecurity and privacy. Moreover, many healthcare data management system applications have emerged, offering solutions for distinct circumstances. But still, theexisting system has issues with specific security issues, privacy-preserving rate,information loss, etc. Hence, the overall system performance is reduced significantly. A unique blockchain-based technique is proposed to improve anonymityin terms of data access and data privacy to overcome the above-mentioned issues.Initially, the registration phase is done for the device and the user. After that, theGeo-Location and IP Address values collected during registration are convertedinto Hash values using Adler 32 hashing algorithm, and the private and publickeys are generated using the key generation centre. Then the authentication is performed through login. The user then submits a request to the blockchain server,which redirects the request to the associated IoT device in order to obtain thesensed IoT data. The detected data is anonymized in the device and stored inthe cloud server using the Linear Scaling based Rider Optimization algorithmwith integrated KL Anonymity (LSR-KLA) approach. After that, the Time-stamp-based Public and Private Key Schnorr Signature (TSPP-SS) mechanismis used to permit the authorized user to access the data, and the blockchain servertracks the entire transaction. The experimental findings showed that the proposedLSR-KLA and TSPP-SS technique provides better performance in terms of higherprivacy-preserving rate, lower information loss, execution time, and Central Processing Unit (CPU) usage than the existing techniques. Thus, the proposed method allows for better data privacy in the smart healthcare network.

The Effects of Turbulence Intensity and Tip Speed Ratio on the Coherent Structure of Horizontal-Axis Wind Turbine Wake:A Wind Tunnel Experiment

The evolution laws of the large-eddy coherent structure of the wind turbine wake have been evaluated via wind tunnel experiments under uniform and turbulent inflow conditions.The spatial correlation coefficients,the turbulence integral scales and power spectrum are obtained at different tip speed ratios(TSRs)based on the time-resolved particle image velocity(TR-PIV)technique.The results indicate that the large-eddy coherent structures are more likely to dissipate with an increase in turbulence intensity and TSR.Furthermore,the spatial correlation of the longitudinal pulsation velocity is greater than its axial counterpart,resulting into a wake turbulence dominated by the longitudinal pulsation.With an increase of turbulence intensity,the integral scale of the axial turbulence increases,meanwhile,its longitudinal counterpart decreases.Owing to an increase in TSR,the integral scale of axial turbulence decreases,whereas,that of the longitudinal turbulence increases.By analyzing the wake power spectrum,it is found that the turbulent pulsation kinetic energy of the wake structure is mainly concentrated in the low-frequency vortex region.The dissipation rate of turbulent kinetic energy increases with an increase of turbulence intensity and the turbulence is transported and dissipated on a smaller scale vortex,thus promoting the recovery of wake.

ASIC Design of Floating-Point FFT Processor

An application specific integrated circuit (ASIC) design of a 1024 points floating-point fast Fourier transform(FFT) processor is presented. It can satisfy the requirement of high accuracy FFT result in related fields. Several novel design techniques for floating-point adder and multiplier are introduced in detail to enhance the speed of the system. At the same time, the power consumption is decreased. The hardware area is effectively reduced as an improved butterfly processor is developed. There is a substantial increase in the performance of the design since a pipelined architecture is adopted, and very large scale integrated (VLSI) is easy to realize due to the regularity. A result of validation using field programmable gate array (FPGA) is shown at the end. When the system clock is set to 50 MHz, 204.8 μs is needed to complete the operation of FFT computation.

Reduced bit low power VLSI architectures for motion estimation

Low power and real time very large scale integration （VLSI） architectures of motion estimation （ME） algorithms for mobile devices and applications are presented. The power reduction is achieved by devising a novel correction recovery mechanism based on algorithms which allow the use of reduced bit sum of absolute difference （RBSAD） metric for calculating matching error and conversion to full resolution sum of absolute difference （SAD） metric whenever necessary. Parallel and pipelined architectures for high throughput of full search ME corresponding to both the full resolution SAD and the generalized RBSAD algorithm are synthe- sized using Xilinx Synthesis Tools （XST）, where the ME designs based on reduced bit （RB） algorithms demonstrate the reduction in power consumption up to 45% and/or the reduction in area up to 38%.

RF-TSV DESIGN, MODELING AND APPLICATION FOR 3D MULTI-CORE COMPUTER SYSTEMS

The state-of-the-art multi-core computer systems are based on Very Large Scale three Dimensional (3D) Integrated circuits (VLSI). In order to provide high-speed vertical data transmission in such 3D systems, efficient Through-Silicon Via (TSV) technology is critically important. In this paper, various Radio Frequency (RF) TSV designs and models are proposed. Specifically, the Cu-plug TSV with surrounding ground TSVs is used as the baseline structure. For further improvement, the dielectric coaxial and novel air-gap coaxial TSVs are introduced. Using the empirical parameters of these coaxial TSVs, the simulation results are obtained demonstrating that these coaxial RF-TSVs can provide two-order higher of cut-off frequencies than the Cu-plug TSVs. Based on these new RF-TSV technologies, we propose a novel 3D multi-core computer system as well as new architectures for manipulating the interfaces between RF and baseband circuit. Taking into consideration the scaling down of IC manufacture technologies, predictions for the performance of future generations of circuits are made. With simulation results indicating energy per bit and area per bit being reduced by 7% and 11% respectively, we can conclude that the proposed method is a worthwhile guideline for the design of future multi-core computer ICs.

Architectural Design of 32 Bit Polar Encoder

The rapid development in the digital circuit design enhances the applications on very large scale integration era. Encoders are one among the digital circuits found in all communication systems. The polar encoding is mainly meant for its channel achieving property. It finds its application in communications, sensing and information theory. This coding proposed by Erdal Arikan is significant because of its zero error floors and simple architecture for hardware implementation. In this paper, a folded polar encoder is designed to start from the fully parallel architecture and proceeds with its data flow graph, delay requirement calculation, lifetime analysis and register allocation, which results in a very large scale integration architecture with minimum hardware utilization. The results are simulated for 4 and 8 parallel folded 32-bit polar encoder using Xilinx 14.6 ISIM and implemented in Virtex 5 field programmable gate array. A comparison is made on fully parallel and various folding techniques based on their resource utilization.

Design and Implementation of an Efficient Reversible Comparator Using TR Gate

Reversible logic is a new emerging technology with many promising applications in optical information processing, low power (Complementary Metal Oxide Semiconductor) CMOS design, (De Oxy RiboNucleic Acid) DNA computing, etc. In industrial automation, comparators play an important role in segregating faulty patterns from good ones. In previous works, these comparators have been implemented with more number of reversible gates and computational complexity. All these comparators use propagation technique to compare the data. This will reduce the efficiency of the comparators. To overcome the problem, this paper proposes an efficient comparator using (Thapliyal Ranganathan) TR gate utilizing full subtraction and half subtraction algorithm which will improve the computation efficiency. The comparator design using half subtraction algorithm shows an improvement in terms of quantum cost. The comparator design using full subtraction algorithm shows effectiveness in reducing number of reversible gates required and garbage output.

Effect of electric field on metallic SWCNT interconnects for nanoscale technologies

The influence of an electric field on metallic single walled carbon nanotube （SWCNT） interconnects is studied. A voltage-dependent equivalent circuit model is presented for the impedance parameters of single-wall carbon nanotubes that capture various electron-phonon scattering mechanisms as a function of the electric field. To estimate the performance of SWCNT bundle interconnects, signal delay and power dissipation are calculated based on the field dependent model that results in an improvement in the delay and power estimation accuracy compared to the field-independent model. We find that the power delay product of a SWCNT bundle increases with the increase in electric field but decreases with technology scaling showing that at a low electric field, the SWCNT bundle is a potential reliable alternative interconnect for future high performance VLSI industry at scaled technologies.

Effects of Dummy Thermal Vias on Interconnect Delay and Power Dissipation of Very Large Scale Integration Circuits

The interconnect temperature of very large scale integration（VLSI） circuits keeps rising due to self-heating and substrate temperature, which can increase the delay and power dissipation of interconnect wires. The thermal vias are regarded as a promising method to improve the temperature performance of VLSI circuits. In this paper, the extra thermal vias were used to decrease the delay and power dissipation of interconnect wires of VLSI circuits. Two analytical models were presented for interconnect temperature, delay and power dissipation with adding extra dummy thermal vias. The influence of the number of thermal vias on the delay and power dissipation of interconnect wires was analyzed and the optimal via separation distance was investigated. The experimental results show that the adding extra dummy thermal vias can reduce the interconnect average temperature, maximum temperature, delay and power dissipation. Moreover, this method is also suitable for clock signal wires with a large root mean square current.

Evaluation of criterion validity of CHF-quality of life scale of integrative medicine

Objective To evaluate the criterion validity of Chronic Heart Failure(CHF)-Quality of Life(QOL)Scale of Integrative Medicine(abbreviated as Scale).Methods Clinical data of 249 CHF in-patients were collected.

Wind Gust and Turbulence Statistics of Typhoons in South China

The wind data of four typhoons were obtained and analyzed. The wind speeds were measured by sonic anemometers at four observation sites in Guangdong and Hainan provinces. Detailed analysis of the wind data was conducted to investigate the turbulence characteristics of the typhoons. Characteristics of the gust factor and the turbulence integral scale of the typhoons were concluded with high confidence. The relationships among the gust factor, gust duration time, mean wind speed, roughness length, and turbulence intensity were described. The turbulence integral scale was found to be closely related to the segment length and turbulence intensity.

Deterministic Circular Self Test Path

Circular self test path (CSTP) is an attractive technique for testing digital integrated circuits(IC) in the nanometer era, because it can easily provide at-speed test with small test data volume and short test application time. However, CSTP cannot reliably attain high fault coverage because of difficulty of testing random-pattern-resistant faults. This paper presents a deterministic CSTP (DCSTP) structure that consists of a DCSTP chain and jumping logic, to attain high fault coverage with low area overhead. Experimental re- sults on ISCAS’89 benchmarks show that 100% fault coverage can be obtained with low area overhead and CPU time, especially for large circuits.

Efficient Statistical Leakage Power Analysis Method for Function Blocks Considering All Process Variations

With technology scaling into nanometer regime, rampant process variations impact visible influences on leakage power estimation of very large scale integrations (VLSIs). In order to deal with the case of large inter- and intra-die variations, we induce a novel theory prototype of the statistical leakage power analysis (SLPA) for function blocks. Because inter-die variations can be pinned down into a small range but the number of gates in function blocks is large(>1000), we continue to simplify the prototype. At last, we induce the efficient methodology of SLPA. The method can save much running time for SLPA in the low power design since it is of the local-updating advantage. A large number of experimental data show that the method only takes feasible running time (0.32 s) to obtain accurate results (3 σ-error <0.5% on maximum) as function block circuits simultaneous suffer from 7.5%(3 σ/mean) inter-die and 7.5% intra-die length variations, which demonstrates that our method is suitable for statistical leakage power analysis of VLSIs under rampant process variations.

Fast VLSI Implementation of Modular Inversion in Galois Field GF(p)

Modular inversion is one of the key arithmetic operations in public key cryptosystems, so low-cost, high-speed hardware implementation is absolutely necessary. This paper presents an algorithm for prime fields for hardware implementation. The algorithm involves only ordinary addition/subtraction and does not need any modular operations, multiplications or divisions. All of the arithmetic operations in the algorithm can be accomplished by only one adder, so it is very suitable for fast very large scale integration (VLSI) implementation. The VLSI implementation of the algorithm is also given with good performance and low silicon penalty.

Incremental Placement-Based Clock Network Minimization Methodology

Power is the major challenge threatening the progress of very large scale integration （VLSI） technology development. In ultra-deep submicron VLSI designs, clock network size must be minimized to reduce power consumption, power supply noise, and the number of clock buffers which are vulnerable to process variations. Traditional design methodologies usually let the clock router independently undertake the clock network minimization. Since clock routing is based on register locations, register placement actually strongly influences the clock network size. This paper describes a clock network design methodology that optimizes register placement. For a given cell placement result, incremental modifications are performed based on the clock skew specifications by moving registers toward preferred locations that may reduce the clock network size. At the same time, the side-effects to logic cell placement, such as signal net wirelength and critical path delay, are controlled. Test results on benchmark circuits show that the methodology can considerably reduce clock network size with limited impact on signal net wirelength and critical path delay.

A novel interconnect optimal buffer insertion model considering the self-heating effect

Considering the self-heating effect, an accurate expression for the global interconnection resistance per unit length in terms of interconnection wire width and spacing is presented. Based on the proposed resistance model and according to the trade-off theory, a novel optimization analytical model of delay, power dissipation and bandwidth is derived. The proposed optimal model is verified and compared based on 90 nm, 65 nm and 40 nm CMOS technologies. It can be found that more optimum results can be easily obtained by the proposed model. This optimization model is more accurate and realistic than the conventional optimization models, and can be integrated into the global interconnection design ofnano-scale integrated circuits.

Efficient Clustering and Simulated Annealing Approach for Circuit Partitioning

Circuit net list bipartitioning using simulated annealing technique has been proposed in the paper.The method converges asymptotically and probabilistically to global optimization.The circuit net list is partitioned into two partitions such that the number of interconnections between the partitions is minimized.The proposed method begins with an innovative clustering technique to obtain a good initial solution.Results obtained show the versatility of the proposed method in solving non polynomial hard problems of circuit net list partitioning and show an improvement over those available in literature.