Pixelated non-volatile programmable photonic integrated circuits with 20-level intermediate states

Multi-level programmable photonic integrated circuits(PICs)and optical metasurfaces have gained widespread attention in many fields,such as neuromorphic photonics,opticalcommunications,and quantum information.In this paper,we propose pixelated programmable Si_(3)N_(4)PICs with record-high 20-level intermediate states at 785 nm wavelength.Such flexibility in phase or amplitude modulation is achieved by a programmable Sb_(2)S_(3)matrix,the footprint of whose elements can be as small as 1.2μm,limited only by the optical diffraction limit of anin-house developed pulsed laser writing system.We believe our work lays the foundation for laser-writing ultra-high-level(20 levels and even more)programmable photonic systems and metasurfaces based on phase change materials,which could catalyze diverse applications such as programmable neuromorphic photonics,biosensing,optical computing,photonic quantum computing,and reconfigurable metasurfaces.

2024 IEEE International Conference on Integrated Circuits,Technologies and Applications

October 25-27(Fri-Sun),2024 Hangzhou杭州,Hangzhou,China Call for Papers The 7th IEEE International Conference on Integrated Circuits,Technologies and Applications(ICTA 2024),will be held on October 25-27,2024 in Hangzhou,China.This conference will be held in China to provide an international forum according to IEEE standard for the presentation and exchange of the latest technical achievements and cross-discipline fertilization of IC designs,technologies,and applications in our fast-changing society.This year's theme is“Chiplet and Future IDM”.

Study on Si-SiGe Three-Dimensional CMOS Integrated Circuits

Based on the physical characteristics of SiGe material,a new three-dimensional （3D） CMOS IC structure is proposed,in which the first device layer is made of Si material for nMOS devices and the second device layer is made of Six Ge1- x material for pMOS. The intrinsic performance of ICs with the new structure is then limited by Si nMOS.The electrical characteristics of a Si-SiGe 3D CMOS device and inverter are all simulated and analyzed by MEDICI. The simulation results indicate that the Si-SiGe 3D CMOS ICs are faster than the Si-Si 3D CMOS ICs. The delay time of the 3D Si-SiGe CMOS inverter is 2-3ps,which is shorter than that of the 3D Si-Si CMOS inverter.

Carbon nanotube integrated circuit technology:purification,assembly and integration

As the manufacturing process of silicon-based integrated circuits(ICs)approaches its physical limit,the quantum effect of silicon-based field-effect transistors(FETs)has become increasingly evident.And the burgeoning carbon-based semiconductor technology has become one of the most disruptive technologies in the post-Moore era.As one-dimensional nanomaterials,carbon nanotubes(CNTs)are far superior to silicon at the same technology nodes of FETs because of their excellent electrical transport and scaling properties,rendering them the most competitive material in the next-generation ICs technology.However,certain challenges impede the industrialization of CNTs,particularly in terms of material preparation,which significantly hinders the development of CNT-based ICs.Focusing on CNT-based ICs technology,this review summarizes its main technical status,development trends,existing challenges,and future development directions.

MET receptor tyrosine kinase promotes the generation of functional synapses in adult cortical circuits

Loss of synapse and functional connectivity in brain circuits is associated with aging and neurodegeneration,however,few molecular mechanisms are known to intrinsically promote synaptogenesis or enhance synapse function.We have previously shown that MET receptor tyrosine kinase in the developing cortical circuits promotes dendritic growth and dendritic spine morphogenesis.To investigate whether enhancing MET in adult cortex has synapse regenerating potential,we created a knockin mouse line,in which the human MET gene expression and signaling can be turned on in adult(10–12 months)cortical neurons through doxycycline-containing chow.We found that similar to the developing brain,turning on MET signaling in the adult cortex activates small GTPases and increases spine density in prefrontal projection neurons.These findings are further corroborated by increased synaptic activity and transient generation of immature silent synapses.Prolonged MET signaling resulted in an increasedα-amino-3-hydroxy-5-methyl-4-isoxazolepropionic acid/N-methyl-Daspartate(AMPA/NMDA)receptor current ratio,indicative of enhanced synaptic function and connectivity.Our data reveal that enhancing MET signaling could be an interventional approach to promote synaptogenesis and preserve functional connectivity in the adult brain.These findings may have implications for regenerative therapy in aging and neurodegeneration conditions.

Cohort study on the treatment of BRAF V600E mutant metastatic colorectal cancer with integrated Chinese and western medicine

BACKGROUND Patients with BRAF V600E mutant metastatic colorectal cancer(mCRC)have a low incidence rate,poor biological activity,suboptimal response to conventional treatments,and a poor prognosis.In the previous cohort study on mCRC conducted by our team,it was observed that integrated Chinese and Western medicine treatment could significantly prolong the overall survival(OS)of patients with colorectal cancer.Therefore,we further explored the survival benefits in the population with BRAF V600E mutant mCRC.AIM To evaluate the efficacy of integrated Chinese and Western medicine in the treatment of BRAF V600E mutant metastatic colorectal cancer.METHODS A cohort study was conducted on patients with BRAF V600E mutant metastatic colorectal cancer admitted to Xiyuan Hospital of China Academy of Chinese Medical Sciences and Traditional Chinese Medicine Hospital of Xinjiang Uygur Autonomous Region from January 2016 to December 2022.The patients were divided into two cohorts.RESULTS A total of 34 cases were included,with 23 in Chinese-Western medicine cohort(cohort A)and 11 in Western medicine cohort(cohort B).The median overall survival was 19.9 months in cohort A and 14.2 months in cohort B,with a statistically significant difference(P=0.038,hazard ratio=0.46).The 1-3-year survival rates were 95.65%(22/23),39.13%(9/23),and 26.09%(6/23)in cohort A,and 63.64%(7/11),18.18%(2/11),and 9.09%(1/11)in cohort B,respectively.Subgroup analysis showed statistically significant differences in median OS between the two cohorts in the right colon,liver metastasis,chemotherapy,and first-line treatment subgroups(P<0.05).CONCLUSION Integrated Chinese and Western medicine can prolong the survival and reduce the risk of death in patients with BRAF V600E mutant metastatic colorectal cancer,with more pronounced benefits observed in patients with right colon involvement,liver metastasis,combined chemotherapy,and first-line treatment.

Emerging MoS_(2)Wafer-Scale Technique for Integrated Circuits

As an outstanding representative of layered materials,molybdenum disulfide(MoS_(2))has excellent physical properties,such as high carrier mobility,stability,and abundance on earth.Moreover,its reasonable band gap and microelectronic compatible fabrication characteristics makes it the most promising candidate in future advanced integrated circuits such as logical electronics,flexible electronics,and focal-plane photodetector.However,to realize the all-aspects application of MoS_(2),the research on obtaining high-quality and large-area films need to be continuously explored to promote its industrialization.Although the MoS_(2)grain size has already improved from several micrometers to sub-millimeters,the high-quality growth of wafer-scale MoS_(2)is still of great challenge.Herein,this review mainly focuses on the evolution of MoS_(2)by including chemical vapor deposition,metal–organic chemical vapor deposition,physical vapor deposition,and thermal conversion technology methods.The state-of-the-art research on the growth and optimization mechanism,including nucleation,orientation,grain,and defect engineering,is systematically summarized.Then,this review summarizes the wafer-scale application of MoS_(2)in a transistor,inverter,electronics,and photodetectors.Finally,the current challenges and future perspectives are outlined for the wafer-scale growth and application of MoS_(2).

Total ionizing dose effect modeling method for CMOS digital-integrated circuit

Simulating the total ionizing dose(TID)of an electrical system using transistor-level models can be difficult and expensive,particularly for digital-integrated circuits(ICs).In this study,a method for modeling TID effects in complementary metaloxide semiconductor(CMOS)digital ICs based on the input/output buffer information specification(IBIS)was proposed.The digital IC was first divided into three parts based on its internal structure:the input buffer,output buffer,and functional area.Each of these three parts was separately modeled.Using the IBIS model,the transistor V-I characteristic curves of the buffers were processed,and the physical parameters were extracted and modeled using VHDL-AMS.In the functional area,logic functions were modeled in VHDL according to the data sheet.A golden digital IC model was developed by combining the input buffer,output buffer,and functional area models.Furthermore,the golden ratio was reconstructed based on TID experimental data,enabling the assessment of TID effects on the threshold voltage,carrier mobility,and time series of the digital IC.TID experiments were conducted using a CMOS non-inverting multiplexer,NC7SZ157,and the results were compared with the simulation results,which showed that the relative errors were less than 2%at each dose point.This confirms the practicality and accuracy of the proposed modeling method.The TID effect model for digital ICs developed using this modeling technique includes both the logical function of the IC and changes in electrical properties and functional degradation impacted by TID,which has potential applications in the design of radiation-hardening tolerance in digital ICs.

Through-silicon-via crosstalk model and optimization design for three-dimensional integrated circuits

Through-silicon-via （TSV） to TSV crosstalk noise is one of the key factors affecting the signal integrity of three- dimensional integrated circuits （3D ICs）. Based on the frequency dependent equivalent electrical parameters for the TSV channel, an analytical crosstalk noise model is established to capture the TSV induced crosstalk noise. The impact of various design parameters including insulation dielectric, via pitch, via height, silicon conductivity, and terminal impedance on the crosstalk noise is analyzed with the proposed model. Two approaches are proposed to alleviate the TSV noise, namely, driver sizing and via shielding, and the SPICE results show 241 rnV and 379 mV reductions in the peak noise voltage, respectively.

High density Al2O3/TaN-based metal-insulatormetal capacitors in application to radio equency integrated circuits

Metal-insulator-metal （MIM） capacitors with atomic-layer-deposited Al2O3 dielectric and reactively sputtered TaN electrodes in application to radio frequency integrated circuits have been characterized electrically. The capacitors exhibit a high density of about 6.05 fF/μm^2, a small leakage current of 4.8 × 10^-8 A/cm^2 at 3 V, a high breakdown electric field of 8.61 MV/cm as well as acceptable voltage coefficients of capacitance （VCCs） of 795 ppm/V2 and 268ppm/V at 1 MHz. The observed properties should be attributed to high-quality Al2O3 film and chemically stable TaN electrodes. Further, a logarithmically linear relationship between quadratic VCC and frequency is observed due to the change of relaxation time with carrier mobility in the dielectric. The conduction mechanism in the high field ranges is dominated by the Poole-Frenkel emission, and the leakage current in the low field ranges is likely to be associated with trap-assisted tunnelling. Meanwhile, the Al2O3 dielectric presents charge trapping under low voltage stresses, and defect generation under high voltage stresses, and it has a hard-breakdown performance.

A 330-500 GHz Zero-Biased Broadband Tripler Based on Terahertz Monolithic Integrated Circuits

A 330-500 GHz zero-biased broadband monolithic integrated tripler is reported. The measured results show that the maximum efficiency and the maximum output power are 2% and 194μW at 348 GHz. The saturation characteristic test shows that the output i dB compression point is about -8.5 dBm at 334 GHz and the maximum efficiency is obtained at the point, which is slightly below the 1 dB compression point. Compared with the conventional hybrid integrated circuit, a major advantage of the monolithic integrated circuit is the significant improvement of reliability and consistency. In this work, a terahertz monolithic frequency multiplier at this band is designed and fabricated.

Hybrid material integration in silicon photonic integrated circuits

Hybrid integration ofⅢ-Ⅴand ferroelectric materials is being broadly adopted to enhance functionalities in silicon photonic integrated circuits(PICs).Bonding and transfer printing have been the popular approaches for integration of III–V gain media with silicon PICs.Similar approaches are also being considered for ferroelectrics to enable larger RF modulation bandwidths,higher linearity,lower optical loss integrated optical modulators on chip.In this paper,we review existing integration strategies ofⅢ-Ⅴmaterials and present a route towards hybrid integration of bothⅢ-Ⅴand ferroelectrics on the same chip.We show that adiabatic transformation of the optical mode between hybrid ferroelectric and silicon sections enables efficient transfer of optical modal energies for maximum overlap of the optical mode with the ferroelectric media,similar to approaches adopted to maximize optical overlap with the gain section,thereby reducing lasing thresholds for hybridⅢ-Ⅴintegration with silicon PICs.Preliminary designs are presented to enable a foundry compatible hybrid integration route of diverse functionalities on silicon PICs.

Science Letters:The Moore’s Law for photonic integrated circuits

We formulate a “Moore’s law” for photonic integrated circuits (PICs) and their spatial integration density using two methods. One is decomposing the integrated photonics devices of diverse types into equivalent basic elements, which makes a comparison with the generic elements of electronic integrated circuits more meaningful. The other is making a complex compo- nent equivalent to a series of basic elements of the same functionality, which is used to calculate the integration density for func- tional components realized with different structures. The results serve as a benchmark of the evolution of PICs and we can con- clude that the density of integration measured in this way roughly increases by a factor of 2 per year. The prospects for a continued increase of spatial integration density are discussed.

Influence of Tilted Angle on Effective Linear Energy Transfer in Single Event Effect Tests for Integrated Circuits at 130 nm Technology Node

A heavy-ion irradiation experiment is studied in digital storage cells with different design approaches in 130？nm CMOS bulk Si and silicon-on-insulator （SOI） technologies. The effectiveness of linear energy transfer （LET） with a tilted ion beam at the 130？nm technology node is obtained. Tests of tilted angles θ=0 ° , 30 ° and 60 ° with respect to the normal direction are performed under heavy-ion Kr with certain power whose LET is about 40？MeVcm 2 /mg at normal incidence. Error numbers in D flip-flop chains are used to determine their upset sensitivity at different incidence angles. It is indicated that the effective LETs for SOI and bulk Si are not exactly in inverse proportion to cosθ , furthermore the effective LET for SOI is more closely in inverse proportion to cosθ compared to bulk Si, which are also the well known behavior. It is interesting that, if we design the sample in the dual interlocked storage cell approach, the effective LET in bulk Si will look like inversely proportional to cosθ very well, which is also specifically explained.

Integrated Experimental and Simulation Investigation of Breakdown Voltage Characteristics Across Electrode Configurations in SF_(6) Circuit Breakers

This study investigates the breakdown voltage characteristics in sulfur hexafluoride(SF6)circuit breakers,employing a novel approach that integrates both experimental investigations and finite element simulations.Utilizing a sphere-sphere electrode configuration,we meticulously measured the relationship between breakdown voltage and electrode gap distances ranging from 1 cm to 4.5 cm.Subsequent simulations,conducted using COMSOL Multiphysics,mirrored the experimental setup to validate the model’s accuracy through a comparison of the breakdown voltage-electrode gap distance curves.The simulation results not only aligned closely with the experimental data but also allowed the extraction of detailed electric field strength,electric potential contours,and electric current flow curves at the breakdown voltage for gap distances extending from 1 to 4.5 cm.Extending the analysis,the study explored the electric field and potential distribution at a constant voltage of 72.5 kV for gap distances between 1 to 10 cm,identifying the maximum electric field strength.A comprehensive comparison of five different electrode configurations(sphere-sphere,sphere-rod,sphere-plane,rod-plane,rod-rod)at 72.5 kV and a gap distance of 1.84 cm underscored the significant influence of electrode geometry on the breakdown process.Moreover,the research contrasts the breakdown voltage in SF6 with that in air,emphasizing SF6’s superior insulating properties.This investigation not only elucidates the intricate dynamics of electrical breakdown in SF6 circuit breakers but also contributes valuable insights into the optimal electrode configurations and the potential for alternative insulating gases,steering future advancements in high-voltage circuit breaker technology.

Efficient thermal analysis method for large scale compound semiconductor integrated circuits based on heterojunction bipolar transistor

In this paper, an efficient thermal analysis method is presented for large scale compound semiconductor integrated circuits based on a heterojunction bipolar transistor with considering the change of thermal conductivity with temperature.The influence caused by the thermal conductivity can be equivalent to the increment of the local temperature surrounding the individual device. The junction temperature for each device can be efficiently calculated by the combination of the semianalytic temperature distribution function and the iteration of local temperature with high accuracy, providing a temperature distribution for a full chip. Applying this method to the InP frequency divider chip and the GaAs analog to digital converter chip, the computational results well agree with the results from the simulator COMSOL and the infrared thermal imager respectively. The proposed method can also be applied to thermal analysis in various kinds of semiconductor integrated circuits.

Device Physics Research for Submicron and Deep Submicron Space Microelectronics Devices and Integrated Circuits

Device physics research for submicron and deep submicron space microelectronics devices and integrated circuits will be described in three topics.1.Thin film submicron and deep submicron SOS / CMOS devices and integrated circuits.2.Deep submicron LDD CMOS devices and integrated circuits.3.C band and Ku band microwave GaAs MESFET and III-V compound hetrojunction HEM T and HBT devices and integrated circuits.

Digital synthesis of programmable photonic integrated circuits

Programmable photonic waveguide meshes can be programmed into many different circuit topologies and thereby provide a variety of functions.Due to the complexity of the signal routing in a general mesh,a particular synthesis algorithm often only accounts for a specific function with a specific cell configuration.In this paper,we try to synthesize the programmable waveguide mesh to support multiple configurations with a more general digital signal processing platform.To show the feasibility of this technique,photonic waveguide meshes in different configurations(square,triangular and hexagonal meshes)are designed to realize optical signal interleaving with arbitrary duty cycles.The digital signal processing(DSP)approach offers an effective pathway for the establishment of a general design platform for the software-defined programmable photonic integrated circuits.The use of well-developed DSP techniques and algorithms establishes a link between optical and electrical signals and makes it convenient to realize the computer-aided design of optics–electronics hybrid systems.

Development of 0.50μm CMOS Integrated Circuits Technology

Submicron CMOS IC technology, including triple layer resist lithography technology, RIE, LDD, Titanium Salicide, shallow junction, thin gate oxide, no bird's beak isolation and channel's multiple implantation doping technology have been developed. 0.50μm. CMOS integrated circuits have been fabricated using this submicron CMOS process.

Development of Physical Library for Short Channel CMOS / SOI Integrated Circuits

An 'Integrated Device and Circuit simulator' for thin film (0.05-0.2μm) submicron (0.5μm) and deep submicron (0.15, 0.25,0.35μm) CMOS/ SOI integrated circuit has been developed. This simulator has been used for design and fabrication and physical library development of thin film submicron and deep submicron CMOS/ SOI integrated circuit.