On-chip interconnect buses consume tens of percents of dynamic power in a nanometer scale integrated circuit and they will consume more power with the rapid scaling down of technology size and continuously rising cloc...On-chip interconnect buses consume tens of percents of dynamic power in a nanometer scale integrated circuit and they will consume more power with the rapid scaling down of technology size and continuously rising clock frequency, therefore it is meaningful to lower the interconnecting bus power in design. In this paper, a simple yet accurate interconnect parasitic capacitance model is presented first and then, based on this model, a novel interconnecting bus optimization method is proposed. Wire spacing is a process for spacing wires for minimum dynamic power, while wire ordering is a process that searches for wire orders that maximally enhance it. The method, i.e., combining wire spacing with wire ordering, focuses on bus dynamic power optimization with a consideration of bus performance requirements. The optimization method is verified based on various nanometer technology parameters, showing that with 50% slack of routing space, 25.71% and 32.65% of power can be saved on average by the proposed optimization method for a global bus and an intermediate bus, respectively, under a 65-nm technology node, compared with 21.78% and 27.68% of power saved on average by uniform spacing technology. The proposed method is especially suitable for computer-aided design of nanometer scale on-chip buses.展开更多
The behavior of quantum cellular automata （QCA） under the influence of a stray charge is quantified. A new time-independent switching paradigm, a probability model of the double-dot system, is developed. Superiority...The behavior of quantum cellular automata （QCA） under the influence of a stray charge is quantified. A new time-independent switching paradigm, a probability model of the double-dot system, is developed. Superiority in releasing the calculation operation is presented by the probability model compared to previous stray charge analysis utilizing ICHA or full-basis calculation. Simulation results illustrate that there is a 186-nm-wide region surrounding a QCA wire where a stray charge will cause the target cell to switch unsuccessfully. The failure is exhibited by two new states＇ dominating the target cell. Therefore, a bistable saturation model is no longer applicable for stray charge analysis.展开更多
智能软开关(Soft Open Points,SOP)的普及使得多台区联合运行成为趋势。针对大规模户用光伏接入低压配电网带来的电压越限、网损和三相不平衡问题,提出一种基于SOP的柔性互联两阶段优化控制架构。日前阶段,考虑长时间尺度光伏及负荷功率...智能软开关(Soft Open Points,SOP)的普及使得多台区联合运行成为趋势。针对大规模户用光伏接入低压配电网带来的电压越限、网损和三相不平衡问题,提出一种基于SOP的柔性互联两阶段优化控制架构。日前阶段,考虑长时间尺度光伏及负荷功率,建立以台区Ⅰ、Ⅱ总网损最小、三相不平衡度最小为目标函数的三相四线柔性互联低压配电网优化模型,求取SOP三相功率出力,采用模型凸化的方式降低求解难度。日内阶段,针对光伏及负荷5分钟短时功率扰动带来的电压波动越限问题,基于日前SOP优化结果,利用SOP两侧换流器电压-无功下垂控制方法抑制电压越限问题。仿真结果表明,所提两阶段优化控制策略能够有效抑制高比例光伏并网带来的供电质量问题。此外,为了保障优化结果对比分析的客观性,选取与本文优化参数相近、光伏接入情况与网络模型相同的文献案例进行对比分析。分析结果表明,通过功率在空间上的转移,实现不同交流台区间的功率互济,解决了多个台区存在的电压质量和网损问题,并且控制变量数目更少,综合优化结果更好。展开更多
基金Project supported by the National Natural Science Foundation of China (Grant Nos. 60725415, 60971066, and 61006028)the National High-Tech Program of China (Grant Nos. 2009AA01Z258 and 2009AA01Z260)the National Key Lab Foundation,China (Grant No. ZHD200904)
文摘On-chip interconnect buses consume tens of percents of dynamic power in a nanometer scale integrated circuit and they will consume more power with the rapid scaling down of technology size and continuously rising clock frequency, therefore it is meaningful to lower the interconnecting bus power in design. In this paper, a simple yet accurate interconnect parasitic capacitance model is presented first and then, based on this model, a novel interconnecting bus optimization method is proposed. Wire spacing is a process for spacing wires for minimum dynamic power, while wire ordering is a process that searches for wire orders that maximally enhance it. The method, i.e., combining wire spacing with wire ordering, focuses on bus dynamic power optimization with a consideration of bus performance requirements. The optimization method is verified based on various nanometer technology parameters, showing that with 50% slack of routing space, 25.71% and 32.65% of power can be saved on average by the proposed optimization method for a global bus and an intermediate bus, respectively, under a 65-nm technology node, compared with 21.78% and 27.68% of power saved on average by uniform spacing technology. The proposed method is especially suitable for computer-aided design of nanometer scale on-chip buses.
基金supported by the National Natural Science Foundation of China(No.61172043)the Key Program of Shaanxi Provincial Natural Science for Basic Research(No.2011JZ015)
文摘The behavior of quantum cellular automata （QCA） under the influence of a stray charge is quantified. A new time-independent switching paradigm, a probability model of the double-dot system, is developed. Superiority in releasing the calculation operation is presented by the probability model compared to previous stray charge analysis utilizing ICHA or full-basis calculation. Simulation results illustrate that there is a 186-nm-wide region surrounding a QCA wire where a stray charge will cause the target cell to switch unsuccessfully. The failure is exhibited by two new states＇ dominating the target cell. Therefore, a bistable saturation model is no longer applicable for stray charge analysis.
文摘智能软开关(Soft Open Points,SOP)的普及使得多台区联合运行成为趋势。针对大规模户用光伏接入低压配电网带来的电压越限、网损和三相不平衡问题,提出一种基于SOP的柔性互联两阶段优化控制架构。日前阶段,考虑长时间尺度光伏及负荷功率,建立以台区Ⅰ、Ⅱ总网损最小、三相不平衡度最小为目标函数的三相四线柔性互联低压配电网优化模型,求取SOP三相功率出力,采用模型凸化的方式降低求解难度。日内阶段,针对光伏及负荷5分钟短时功率扰动带来的电压波动越限问题,基于日前SOP优化结果,利用SOP两侧换流器电压-无功下垂控制方法抑制电压越限问题。仿真结果表明,所提两阶段优化控制策略能够有效抑制高比例光伏并网带来的供电质量问题。此外,为了保障优化结果对比分析的客观性,选取与本文优化参数相近、光伏接入情况与网络模型相同的文献案例进行对比分析。分析结果表明,通过功率在空间上的转移,实现不同交流台区间的功率互济,解决了多个台区存在的电压质量和网损问题,并且控制变量数目更少,综合优化结果更好。
