期刊文献+
共找到1篇文章
< 1 >
每页显示 20 50 100
On the design of high-speed energy-efficient successive-approximation logic for asynchronous SAR ADCs
1
作者 Jiaqi Yang Ting Li +3 位作者 Mingyuan Yu Shuangshuang Zhang Fujiang Lin Lin He 《Journal of Semiconductors》 EI CAS CSCD 2017年第8期87-92,共6页
This paper analyzes the power consumption and delay mechanisms of the successive-approximation (SA) logic of a typical asynchronous SAR ADC, and provides strategies to reduce both of them. Following these strategies... This paper analyzes the power consumption and delay mechanisms of the successive-approximation (SA) logic of a typical asynchronous SAR ADC, and provides strategies to reduce both of them. Following these strategies, a unique direct-pass SA logic is proposed based on a full-swing once-triggered DFF and a self-locking tri-state gate. The unnecessary internal switching power of a typical TSPC DFF, which is commonly used in the SA logic, is avoided. The delay of the ready detector as well as the sequencer is removed from the critical path. A prototype SAR ADC based on the proposed SA logic is fabricated in 130 nm CMOS. It achieves a peak SNDR of 56.3 dB at 1.2 V supply and 65 MS/s sampling rate, and has a total power consumption of 555 μW, while the digital part consumes only 203μW. 展开更多
关键词 analog-to-digital conversion successive approximation LOW-POWER HIGH-SPEED internal switchingactivities
原文传递
上一页 1 下一页 到第
使用帮助 返回顶部