INTELLIGENT CONTROL SYSTEM OF PULSED MAG WELDING INVERTER BASED ON DIGITAL SIGNAL PROCESSOR

A fuzzy logic intelligent control system of pulsed MAG welding inverter based on digital signal processor （DSP） is proposed to obtain the consistency of arc length in pulsed MAG welding. The proposed control system combines the merits of intelligent control with DSP digital control. The fuzzy logic intelligent control system designed is a typical two-input-single-output structure, and regards the error and the change in error of peak arc voltage as two inputs and the background time as single output. The fuzzy logic intelligent control system is realized in a look-up table （LUT） method by using MATLAB based fuzzy logic toolbox, and the implement of LUT method based on DSP is also discussed. The pulsed MAG welding experimental results demonstrate that the developed fuzzy logic intelligent control system based on DSP has strong arc length controlling ability to accomplish the stable pulsed MAG welding process and controls pulsed MAG welding inverter digitally and intelligently.

基于双DSP(Digital Signal Processor)结构的有源滤波器检测及控制系统

简要介绍了DigitalSignalProcessor(DSP)的发展及其性能特点 ,详细讨论了一种利用双DSP构成的有源滤波器检测及控制系统的实现和基本结构及算法 .

Digital control of pulsed gas metal arc welding inverter using TMS320LF2407A

A digital control of pulsed gas metal arc welding inverter was proposed. A control system consisting of analogue parts was replaced with a new digital control implemented in a TMS320LF2407A DSP chip. The design and constructional features of the whole digital control were presented. The resources of the DSP chip were efficiently utilized and the circuits are very concise, which can enhance the stability and reliability of welding inverter. Experimental results demonstrate that the developed digital control has the ability to accomplish the excellent pulsed gas metal arc welding process and the merits of the developed digital control are stable welding process, little spatter and perfect weld appearance.

A novel arc welding inverter with unit power factor based on DSP control

A novel inverter power source is developed characterized with constant output current and unit power factor input. Digital signal processor （ DSP ） is used to realize power factor correction and control of back-stage inverter bridge of the arc welding inverter. The fore-stage adopts double closed loop proportion and integration （PI） rectifier technique and the back- stage adopts digital pulse width modulation （ PWM） technique. Simulated waves can be obtained in Matlab/Simulink and validated by experiments. Experiments of the prototype showed that the total harmonic distortion （THD） can be controlled within 10% and the power factor is approximate to 1.

A Real-Time Power Controller for Grid-Connected Inverters in LV Smart Microgrids

This paper presents a real-time power flow controller for VSIs （voltage source inverters） interfaced to low voltage microgrids. The proposed controller is modular, flexible, intelligent, inexpensive, portable, adaptive and designed to positively contribute in low voltage microgrids in which the lines R/X ratio is greater than the transmission lines. Therefore, the proposed control strategy is developed for operation in distribution lines. The controller strategy is different from the conventional grid-connected inverters which are designed based on transmission line characteristics. This controller, using a Texas Instrument general purpose DSP （digital signal processor）, is programmed and tuned using MATLAB/SIMULINK in order to enhance self-healing, reliability and stability of the grid. This general purpose controller makes proper decisions using its local measurements as the primary source of data. The controller has the capability of communicating with the adjacent controllers and sharing the information if/when needed. The power flow output of the inverter is tested for both islanded and grid-connected modes of operation. The inverter positively contributes to active and reactive power supply while operating in grid-connected mode. The proposed control method has been implemented on a Texas Instrument DSC （digital signal controller） chip and tested on a hardware test bench at the Alternative Energy Laboratory at WVU1T （West Virginia University Institute of Technology）. The system＇s experimental results veri~ the validity and efficiency of the proposed controller.

POWER OPTIMIZATION FOR THE DATAPATH OF A 32-BIT RECONFIGURABLE PIPELINED DSP PROCESSOR

With the continuous increasing of circuit scale, the problem of power consumption is paid much more attention than before, especially in large designs. In this paper, an experience of optimizing the power consumption of the 16-bit datapath in a 32-bit reconfigurable pipelined Digital Signal Processor (DSP) is introduced. By keeping the old input values and preventing the useless switching of the logic blocks on the datapath, the power consumption is much lowered. At the same time, by relocating some logic blocks between different pipeline stages and employing some data forward logics, a better balanced pipeline is achieved to lower the power consumption for conditional computation instructions at very low timing and area costs. The effectivity of these power optimization technologies are proved by the experimental results. Finally, some ideas about how to reduce the power consumption of circuits are proposed, which are very effective and useful in practice designs, especially in pipelined ones.

Design of a Low Power DSP with Distributed and Early Clock Gating

A novel clock structure of a low-power 16-bit very large instruction word (VLIW) digital signal processor (DSP) was proposed. To improve deterministic clock gating and to solve the drawback of conventional clock gating circuit in high speed circuit, a distributed and early clock gating method was developed on its instruction fetch & decoder unit, its pipelined data-path unit and its super-Harvard memory interface unit. The core was implemented following the Synopsys back-end flow under TSMC (Taiwan Silicon manufacture corporation) 0.18-μm 1.8-V 1P6M process, with a core size of 2 mm×2 mm. Result shows that it can run under 200 MHz with a power performance around 0.3 mW/MIPS. Meanwhile, only 39.7% circuit is active simultaneously in average, compared to its non-gating counterparts.

Design and implementation of a DSP with multi-level low power strategies for cochlear implants

This paper presents the design and implementation of a low power digital signal processor （THUCIDSP-1 ） targeting at application for cochlear implants. Multi-level low power strategies including algorithm optimization, operand isolation, clock gating and memory partitioning are adopted in the processor design to reduce the power consumption. Experimental results show that the complexity of the Continuous Interleaved Sampling （CIS） algorithm is reduced by more than 80 % and the power dissipation of the hardware alone is reduced by about 25% with the low power methods. The THUCIDSP-1 prototype, fabricated in 0.18-μm standard CMOS process, consumes only 1.91 mW when executing the CIS algorithm at 3 MHz.

Design for Low Power Testing of Computation Modules with Contiguous Subspace in VLSI

A kind of pseudo Gray code presentation of test patterns based on accumulation generators is presented and a low power test scheme is proposed to test computational function modules with contiguous subspace in very large scale integration （VLSI）, especially in digital signal processors （DSP）. If test patterns from accumulators for the modules are encoded in the pseudo Gray code presentation, the switching activities of the modules are reduced, and the decrease of the test power consumption is resulted in. Results of experimentation based on FPGA show that the test approach can reduce dynamic power consumption by an average of 17.40% for 8-bit ripple carry adder consisting of 3-2 counters. Then implementation of the low power test in hardware is exploited. Because of the reuse of adders, introduction of additional XOR logic gates is avoided successfully. The design minimizes additional hardware overhead for test and needs no adjustment of circuit structure. The low power test can detect any combinational stuck-at fault within the basic building block without any degradation of original circuit performance.

HIL Simulation of a Mixed Islanded Power Network with External DSP Regulator

The present paper deals with the development of a modular, flexible and structured block to block approach for the study of regulators by implementing the different blocks on a DSP （digital signal processor）. The proposed low-cost approach has been applied and validated by the implementation of an industrial regulator in a real time hardware-in-the-loop simulation of a mixed islanded power network including precise models of the hydraulic system. The studied network is constituted of three different types of electrical power generation systems and a consumer.

次级路径参数对变压器有源降噪系统性能影响的研究

本文针对电力变压器有源降噪系统的次级路径参数对降噪效果的影响进行研究,提出次级路径时延计算方法。以滤波x最小方均(FxLMS)算法为基础,搭建基于TMS320C6748数字信号处理器(DSP)的变压器有源降噪实验系统,并对比不同次级路径时延下的变压器有源降噪实验效果,就次级路径时延对变压器有源降噪系统降噪性能所造成的影响进行验证。

Z-源逆变器在光伏发电系统中的应用

Z-源逆变器由于采用独特的X型Z-源网络,可以利用逆变器桥臂直通状态实现升压功能,从而使单级Z-源逆变器具有与两级并网系统相类似的性能。该文论述基于Z-源逆变器的光伏并网系统在变换效率、可靠性以及成本方面的优势,提出了一种新的单级Z-源逆变器并网系统两级控制策略,该控制策略实现了MPPT控制和逆变器并网控制,使Z-源光伏并网系统能够动态跟踪光伏电池最大功率点电压,输出电流与电网电压同相位,从而达到较高的功率因数。软件仿真和实验分析证明了该控制方法具有优良的动、静态特性,适合各种变化的天气情况。

电焊机的数字化

逆变技术在焊接电源中的应用使得焊接设备在小型化、高效化的方面有了飞跃性的发展。同时 ,弧焊逆变电源良好的动特性更为焊接工艺控制提供了一个充分发挥的平台。然而 ,传统的模拟控制方式存在的种种弊端却限制了弧焊逆变电源的进一步发展。本文结合数字信号处理技术的特点 ,综合分析了数字化焊机的优点。在此基础上针对电焊机的主电路和控制电路两部分介绍了数字化的发展概况及其实现方式。最后 。

无轴承开关磁阻电机实验平台的设计与实现

将无轴承技术应用于开关磁阻电机中可充分发挥该电机的高速适应性,并拓宽其在微型和大功率领域中的应用。该文在已有数学模型基础上,针对其电磁转矩和悬浮力的控制特点,设计了以DSP-LF2407A为控制核心的数模混合控制实验平台。实验平台包括无轴承开关磁阻电机本体、DSP数字控制器、电流滞环控制器、PID调节单元、3套功率逆变器、传感器和相关辅助电路,并对其工作原理进行了分析。在此基础上设计了控制系统的软件,并给出了主要子程序的流程图。通过对整个实验平台硬软件的联合调试,实现了无轴承开关磁阻电机的稳定悬浮。

一种新的逆变器并网控制策略的研究

提出了一种新的逆变器并网控制策略。可独立与并网双模式运行的逆变器在并网模式下,由于输出滤波电容的影响,在轻载时进网电流ηTHD高,输出功率因数低。该逆变器在传统控制策略的基础上,加入输出滤波电容电流补偿器,消除输出滤波电容电流对电网的影响,从而可以实现独立与并网2模式之间的无缝切换;全负载范围内或电网电压谐波含量大时,可实现高的输出功率因数和低的进网电流ηTHD。该文阐述了该控制策略的工作原理和参数设计原则,并以一台500W基于DSP控制的双降压式半桥逆变器进行了实验验证。

基于数字信号处理器的有源电力滤波器控制方案综述

有源电力滤波器(ActivePowerFilter,APF)是补偿电力系统谐波及无功功率的重要装置,其控制的实时性和准确性是实现有效补偿的一个关键。数字信号处理器(DigitalSignalProcessor,DSP)是一种实时计算速度快、精度高的控制器,能满足APF各种控制方案快速响应的要求,并可有效提高控制系统的实时性和准确性。文章介绍了基于DSP的空间矢量调制、滞环电流控制、单周控制、滑模控制、无差拍控制、重复控制、预测控制、模糊控制以及人工神经网络控制这几种APF控制方案的基本原理,指出了它们各自的优缺点。

400Hz 恒压恒频逆变器的一种模糊-重复混合控制方案(英文)

针对400Hz 恒压恒频(CVCF)逆变器,提出了一种模糊-重复混合控制方案。模糊PD 控制器用于改善系统处于振荡或过冲时的动态性能,重复控制器用于稳态时输出高质量的正弦电压。因此模糊PD 控制器和重复控制器的混合可以利用它们各自的优点,该控制方案采用TI 的DSP 芯片TMS320F240 在一台400Hz、5.5kW 样机上得以实现。实验结果验证了所提出的控制方案不仅能在稳态时获得低THD的输出电压,而且在负载突变时获得了较好的动态性能。

基于DSP的SVPWM的研究

对空间矢量脉宽调制(SVPWM)的理论进行了较详细的讨论。利用DSP电机控制器TMS320F240分别用硬件和软件方式实现了SVPWM,分析了两种方法的优缺点,并给出了相应的实验结果,该方法速度快,精度高。

三相三线有源电力滤波器滞环电流控制策略

滞环电流控制是三相四线有源电力滤波器(APF)常用的电流控制方法,但在三相三线APF中应用不够成熟。分析了三相三线APF滞环电流控制策略的原理及可行性,给出了滞环控制中关键参数的设计和选择方法。通过对开关模态及三相电流关系的分析,推导出了三相三线APF直流侧电压选择的理论参考公式。在此基础上提出一种基于双数字信号处理器的APF数字滞环电流控制方法,实现了全数字化三相三线APF的滞环电流控制,实验结果证明了该方法的有效性。

基于重复控制原理的正弦逆变控制

为提高正弦逆变电源的波形质量和系统动、静态响应性能,在正弦逆变控制中引入重复控制原理。该算法将逆变电源视作一个参考正弦信号的随动系统,建立了单相正弦逆变电源输出滤波单元数学模型,利用Matlab仿真软件对算法进行了在线仿真研究,并利用DSP微控制器构建的实验平台对算法进行了实验验证。结果表明,在采用该算法所设计控制器的控制下,正弦逆变器逆变输出稳定、波形畸变小、静态抗负载干扰能力强。