Low-power switched-capacitor delta-sigma modulator for EEG recording applications

This paper presents a third-order single-loop delta-sigma modulator of a biomedical micro-system for portable electroencephalogram（EEG） monitoring applications.To reduce the power consumption,the loop filter of the proposed modulator is implemented by applying a switched-capacitor structure.The modulator is designed in a 0.35-μm 2P4M standard CMOS process,with an active area of 365×290μm^2.Experimental results show that this modulator achieves a 68 dB dynamic range with an input sinusoidal signal of 100 Hz signal bandwidth under a 64 over-sampling ratio.The whole circuit consumes 515μW under a 2.5 V power supply,which is suitable for portable EEG monitoring.

A large-current, highly integrated switched-capacitor divider with a dual-branch interleaved topology and light load efficiency improvement

Because it is magnet-free and can achieve a high integration level,the switched-capacitor(SC)converter acting as a direct current transformer has many promising applications in modern electronics.However,designing an SC converter with large current capability and high power efficiency is still challenging.This paper proposes a dual-branch SC voltage divider and presents its integrated circuit(IC)implementation.The designed SC converter is capable of driving large current load,thus widening the use of SC converters to high-power applications.This SC converter has a constant conversion ratio of 1/2 and its dual-branch interleaved operation ensures a continuous input current.An effective on-chip gate-driving method using a capacitively coupled floating-voltage level shifter is proposed to drive the all-NMOS power train.Due to the self-powered structure,the flying capacitor itself is also a bootstrap capacitor for gate driving and thus reduces the number of needed components.A digital frequency modulation method is adopted and the switching frequency decreases automatically at light load to improve light load efficiency.The converter IC is implemented using a 180 nm triple-well BCD process.Experimental results verify the effectiveness of the dual-branch interleaved operation and the self-powered gate-driving method.The proposed SC divider can drive up to 4 A load current with 5–12 V input voltage and its power efficiency is as high as 96.5%.At light load,using the proposed optimization method,the power efficiency is improved by 30%.

Switched-capacitor multiply-by-two amplifier with reduced capacitor mismatches sensitivity and full swing sample signal common-mode voltage

A switched-capacitor amplifier with an accurate gain of two that is insensitive to component mismatch is proposed.This structure is based on associating two sets of two capacitors in cross series during the amplification phase.This circuit permits the common-mode voltage of the sample signal to reach full swing.Using the charge-complement technique,the proposed amplifier can reduce the impact of parasitic capacitors on the gain accuracy effectively.Simulation results show that as sample signal common-mode voltage changes,the difference between the minimum and maximum gain error is less than 0.03%.When the capacitor mismatch is increased from 0 to 0.2%,the gain error is deteriorated by 0.00015%）.In all simulations,the gain of amplifier is 69 dB.

An improved single-loop sigma-delta modulator for GSM applications

Traditional feedforward structures suffer from performance constraints caused by the complex adder before quantizer.This paper presents an improved 4th-order 1 -bit sigma-delta modulator which has a simple adder and delayed input feedforward to relax timing constraints and implement low-distortion.The modulator was fabricated in a 0.35μm CMOS process,and it achieved 92.8 dB SNDR and 101 dB DR with a signal bandwidth of 100 kHz dissipating 8.6 mW power from a 3.3-V supply.The performance satisfies the requirements of a GSM system.

Waveform timing performance of a 5 GS/s fast pulse sampling module with DRS4

We first clarify timing issues of non-uniform sampling intervals regarding a 5 GS/s fast pulse sampling module with DRS4. A calibration strategy is proposed, and as a result, the waveform timing performance is improved to below 10 ps RMS. We then further evaluate waveform-timing performance of the module by comparing with a 10 GS/s oscilloscope in a setup with plastic scintillators and fast PMTs. Different waveform timing algorithms are employed for analysis, and the module shows comparable timing performance with that of the oscilloscope.