Design of vertical diamond Schottky barrier diode with junction terminal extension structure by using the n-Ga_(2)O_(3)/p-diamond heterojunction

A novel junction terminal extension structure is proposed for vertical diamond Schottky barrier diodes(SBDs) by using an n-Ga_(2)O_(3)/p-diamond heterojunction. The depletion region of the heterojunction suppresses part of the forward current conduction path, which slightly increases the on-resistance. On the other hand, the reverse breakdown voltage is enhanced obviously because of attenuated electric field crowding. By optimizing the doping concentration, length, and depth of n-Ga_(2)O_(3), the trade-off between on-resistance and breakdown voltage with a high Baliga figure of merit(FOM)value is realized through Silvaco technology computer-aided design simulation. In addition, the effect of the work functions of the Schottky electrodes is evaluated. The results are beneficial to realizing a high-performance vertical diamond SBD.

High performance trench diamond junction barrier Schottky diode with a sidewall-enhanced structure

The trench diamond junction barrier Schottky(JBS)diode with a sidewall enhanced structure is designed by Silvaco simulation.Comparing with the conventional trench JBS diode,Schottky contact areas are introduced on the sidewall of the trench beside the top cathode.The sidewall Schottky contact weakens the junction field-effect transistor effect between the trenches to realize a low on-resistance and a high Baliga's figure of merit(FOM)value.In addition,the existence of the n-type diamond helps to suppress the electric field crowding effect and enhance the reverse breakdown voltage.With the optimal parameters of device structure,a high Baliga's FOM value of 2.28 GW/cm^(2) is designed.Therefore,the proposed sidewall-enhanced trench JBS diode is a promising component for the applications in diamond power electronics.

2.83-kV double-layered NiO/β-Ga_(2)O_(3) vertical p-n heterojunction diode with a power figure-of-merit of 5.98 GW/cm^(2)

This work demonstrates high-performance NiO/β-Ga_(2)O_(3) vertical heterojunction diodes(HJDs)with double-layer junc-tion termination extension(DL-JTE)consisting of two p-typed NiO layers with varied lengths.The bottom 60-nm p-NiO layer fully covers theβ-Ga_(2)O_(3) wafer,while the geometry of the upper 60-nm p-NiO layer is 10μm larger than the square anode elec-trode.Compared with a single-layer JTE,the electric field concentration is inhibited by double-layer JTE structure effectively,resulting in the breakdown voltage being improved from 2020 to 2830 V.Moreover,double p-typed NiO layers allow more holes into the Ga_(2)O_(3) drift layer to reduce drift resistance.The specific on-resistance is reduced from 1.93 to 1.34 mΩ·cm^(2).The device with DL-JTE shows a power figure-of-merit(PFOM)of 5.98 GW/cm^(2),which is 2.8 times larger than that of the conven-tional single-layer JTE structure.These results indicate that the double-layer JTE structure provides a viable way of fabricating high-performance Ga_(2)O_(3) HJDs.

Research on high-voltage 4H-SiC P-i-N diode with planar edge junction termination techniques

The planar edge termination techniques of junction termination extension （JTE） and offset field plates and fieldlimiting rings for the 4H-SiC P i-N diode were investigated and optimized by using a two-dimensional device simulator ISE-TCAD10.0. By experimental verification, a good consistency between simulation and experiment can be observed. The results show that the reverse breakdown voltage for the 4H-SiC P-i-N diode with optimized JTE edge termination can accomplish near ideal breakdown voltage and much lower leakage current. The breakdown voltage can be near 1650 V, which achieves more than 90 percent of ideal parallel plane junction breakdown voltage and the leakage current density can be near 3 ×10^-5 A/cm2.

Simulation study of a mixed terminal structure for 4H-SiC merged PiN/Schottky diode

In this paper, a mixed terminal structure for the 4H-SiC merged PiN/Schottky diode （MPS） is investigated, which is a combination of a field plate, a junction termination extension and floating limiting rings. Optimization is performed on the terminal structure by using the ISE-TCAD. Further analysis shows that this structure can greatly reduce the sensitivity of the breakdown voltage to the doping concentration and can effectively suppress the effect of the interface charge compared with the structure of the junction termination extension. At the same time, the 4H-SiC MPS with this termination structure can reach a high and stable breakdown voltage.

Influence of geometrical parameters on the behaviour of SiC merged PiN Schottky rectifiers with junction termination extension

This paper investigates the behaviours of 4H--SiC merged PiN Schottky （MPS） rectifiers with junction termination extension （JTE） by extensive numerical simulations. The simulated results show that the present model matches the experimental data very well. The influences of the JTE design parameters such as the doping concentration and length of the JTE on the breakdown characteristics are discussed in detail. Then the temperature sensitivity of the forward behaviour is studied in terms of the different designs of 4H--SiC MPS with JTE, which provides a particularly useful guideline for the optimal design of MPS rectifiers with JTE.

Optimal impurity distribution model and experimental verification of variation of lateral doping termination

Based on the charge balance principle,an optimal impurity distribution variation of lateral doping termination(OIDVLD)and its ion-injection mask design method are proposed and verified.The comparative simulations and experiments show that OID-VLD can achieve better blocking ability and reliability than the traditional VLD(T-VLD).Vertical double diffusion MOSFET(VDMOS)with OID-VLD achieved breakdown voltage(BV)of 1684 V and passed the 168 hours 100℃-110℃-120℃-125℃high-temperature reverse bias(HTRB)test,while VDMOS with T-VLD obtained BV of 1636 V and failed in the 20 hours 120℃HTRB test.

Modeling and understanding of the thermal failure induced by high power microwave in CMOS inverter

The thermal failure induced by high power microwave（HPM） in a complementary metal oxide semiconductor（CMOS） inverter is investigated and its dependence on microwave parameters is discussed in detail. An analytical model of the temperature distribution is established and the relationships between hotspot temperature and pulse width and between hotspot temperature and frequency are predicted, which reveals a more severe rise in temperature under the influence of microwave with longer width and lower frequency. The temperature variation mechanism and the theoretical temperature model are validated and explained by the simulation. Furthermore, variation trend of damage threshold with microwave parameters is derived theoretically, and the conclusions are consistent with simulation results and reported data.

Optimization of junction termination extension for ultrahigh voltage 4H-SiC planar power devices

Numerical simulations on the optimization of junction termination extension（JTE） have been performed.Various termination techniques have been applied and simulated in this paper,such as single-zone JTE（S-JTE）,multi-zone JTE（M-JTE）,and space-modulated JTE（SM-JTE）.A completely novel and efficient method is demonstrated in this paper to determine total length of SM-JTE,and it is verified through simulation results.The simulation results show that the SM-JTE could provide a protection efficiency（defined in Section 2） of 95.2%,which is much higher than that of M-JTE（82.4%） and S-JTE（64.7%）.Based on the fabricated MOSFETs,the interface charge density is extracted and the approximate range of charge density has been determined.The influences of different interface charge densities have been investigated for the three termination techniques respectively.According to the previous reports,the JTE is quite sensitive to the implanted dose,so the blocking capability of each termination structure with different implanted doses is also simulated.The results show that when interface charge is considered,the SM-JTE always shows an enormous advantage over the other two junction termination structures,however the interface charge densities varied.The space-modulated JTE is also applicable to the power planar devices such as MOSFETs and IGBTs,which would provide a very promising lower fabrication cost.

Design and optimization of linearly graded-doping junction termination extension for 3.3-kV-class IGBTs

A linearly graded-doping junction termination extension （LG-JTE） for 3.3-kV-class insulated gate bipo- lar transistors （IGBTs） was proposed and experimentally investigated. Unlike conventional multi-implantation uti- lizing more than one photolithography step, a single mask with injection window widths varied linearly away fi＇om the main junction to the edge was implemented in this proposed structure. Based on the simulation results, IGBTs with LG4TE structures were successfully fabricated on the domestic process platform. The fabricated devices exhibited a 3.7 kV forward-blocking voltage, which is close to the theoretical value of an ideal parallel plane case. This is the first success in fabrication 3.3-kV-class 1GBT in a domestic application.

High-voltage 4H-SiC PiN diodes with the etched implant junction termination extension

This paper presents the design and fabrication of an etched implant junction termination extension（JTE）for high-voltage 4H-SiC PiN diodes. Unlike the conventional JTE structure, the proposed structure utilizes multiple etching steps to achieve the optimum JTE concentration range. The simulation results show that the etched implant JTE method can improve the blocking voltage of SiC PiN diodes and also provides broad process latitude for parameter variations, such as implantation dose and activation annealing condition. The fabricated SiC PiN diodes with the etched implant JTE exhibit a highest blocking voltage of 4.5 kV and the forward on-state voltage of 4.6 V at room temperature. These results are of interest for understanding the etched implant method in the fabrication of high-voltage power devices.

Characteristics of blocking voltage for power 4H-SiC BJTs with mesa edge termination

According to the avalanche ionization theory,a computer-based analysis is performed to analyze the structural parameters of single-and multiple-zone junction termination extension（JTE） structures for 4H-SiC bipolar junction transistors（BJTs） with mesa structure.The calculation results show that a single-zone JTE can yield high breakdown voltages if the activated JTE dose and the implantation width are controlled precisely and a multiple-zone JTE method can decrease the peak surface field while still maintaining a high blocking capability.The influences of the positive and negative surface or interface states on the blocking capability are also shown.These conclusions have a realistic meaning in optimizing the design of a mesa power device.