A novel n-type junctionless field-effect transistor(JLFET) with a step-gate-oxide(SGO) structure is proposed to suppress the gate-induced drain leakage(GIDL) effect and off-state current I_(off).Introducing a 6-nm-thi...A novel n-type junctionless field-effect transistor(JLFET) with a step-gate-oxide(SGO) structure is proposed to suppress the gate-induced drain leakage(GIDL) effect and off-state current I_(off).Introducing a 6-nm-thick tunnel-gateoxide and maintaining 3-nm-thick control-gate-oxide,lateral band-to-band tunneling(L-BTBT) width is enlarged and its tunneling probability is reduced at the channel-drain surface,leading the off-state current I_(off) to decrease finally.Also,the thicker tunnel-gate-oxide can reduce the influence on the total gate capacitance of JLFET,which could alleviate the capacitive load of the transistor in the circuit applications.Sentaurus simulation shows that I_(off) of the new optimized JLFET reduced significantly with little impaction on its on-state current Ion and threshold voltage V_(TH) becoming less,thus showing an improved I_(on)/I_(off) ratio(5×10^(4)) and subthreshold swing(84 mV/dec),compared with the scenario of the normal JLFET.The influence of the thickness and length of SGO structure on the performance of JLFET are discussed in detail,which could provide useful instruction for the device design.展开更多
研究了一种新型非对称栅隧穿场效应晶体管(AG-TFET),新型结构结合了隧穿场效应晶体管陡峭的亚阈值摆幅与无结器件较大的开态电流的优点,其总电流大小受控于底部沟道势垒和p+区与本征沟道区形成的反偏p-i隧穿结处的带隙宽度以及电场强度...研究了一种新型非对称栅隧穿场效应晶体管(AG-TFET),新型结构结合了隧穿场效应晶体管陡峭的亚阈值摆幅与无结器件较大的开态电流的优点,其总电流大小受控于底部沟道势垒和p+区与本征沟道区形成的反偏p-i隧穿结处的带隙宽度以及电场强度。使用Silvaco TCAD软件对器件性能进行了仿真,并对p+区厚度以及底栅栅介质二氧化铪的长度进行了优化。仿真结果表明:新型AG-TFET具有良好的电学特性,在室温下开关电流比可以达到3.3×1010,开态电流为302μA/μm,陡峭的亚阈值摆幅即点亚阈值摆幅为35 m V/dec,平均亚阈值摆幅为54 m V/dec。因此,该新型AG-TFET有望被应用在未来低功耗电路中。展开更多
In this study,we fabricate Si/SiGe core-shell Junctionless accumulation mode(JAM)FinFET devices through a rapid and novel process with four main steps,i.e.e-beam lithography definition,sputter deposition,alloy combina...In this study,we fabricate Si/SiGe core-shell Junctionless accumulation mode(JAM)FinFET devices through a rapid and novel process with four main steps,i.e.e-beam lithography definition,sputter deposition,alloy combination annealing,and chemical solution etching.The height of Si core is 30 nm and the thickness of Si/SiGe core-shell is about 2 nm.After finishing the fabrication of devices,we widely studied the electrical characteristics of poly Si/SiGe core-shell JAM FinFET transistors from a view of different Lg and Wch.A poly-Si/SiGe core-shell JAMFETs was successfully demonstrated and it also exhibits a superior subthreshold swing of 81mV/dec and high on/off ratio>10^5 when annealing for 1hr at 600℃.The thermal diffusion process condition for this study are 1hr at 600℃ and 6hr at 700℃ for comparison.The annealing condition at 700oC for 6 hours shows undesired electrical characteristics against the other.Results suggests that from over thermal budget causes a plenty of Ge to precipitate against to form SiGe thin film.Annealing JAMFETs at low temperature shows outstanding Subthreshold swing and better swing condition when compared to its counterpart i.e.at higher temperature.This new process can still fabricate a comparable performance to classical planar FinFET in driving current.展开更多
基金Project supported by the National Natural Science Foundation of China(Grant No.61704130)the Fund from the Science and Technology on Analog Integrated Circuit Laboratory,China(Grant No.JCKY2019210C029)。
文摘A novel n-type junctionless field-effect transistor(JLFET) with a step-gate-oxide(SGO) structure is proposed to suppress the gate-induced drain leakage(GIDL) effect and off-state current I_(off).Introducing a 6-nm-thick tunnel-gateoxide and maintaining 3-nm-thick control-gate-oxide,lateral band-to-band tunneling(L-BTBT) width is enlarged and its tunneling probability is reduced at the channel-drain surface,leading the off-state current I_(off) to decrease finally.Also,the thicker tunnel-gate-oxide can reduce the influence on the total gate capacitance of JLFET,which could alleviate the capacitive load of the transistor in the circuit applications.Sentaurus simulation shows that I_(off) of the new optimized JLFET reduced significantly with little impaction on its on-state current Ion and threshold voltage V_(TH) becoming less,thus showing an improved I_(on)/I_(off) ratio(5×10^(4)) and subthreshold swing(84 mV/dec),compared with the scenario of the normal JLFET.The influence of the thickness and length of SGO structure on the performance of JLFET are discussed in detail,which could provide useful instruction for the device design.
文摘研究了一种新型非对称栅隧穿场效应晶体管(AG-TFET),新型结构结合了隧穿场效应晶体管陡峭的亚阈值摆幅与无结器件较大的开态电流的优点,其总电流大小受控于底部沟道势垒和p+区与本征沟道区形成的反偏p-i隧穿结处的带隙宽度以及电场强度。使用Silvaco TCAD软件对器件性能进行了仿真,并对p+区厚度以及底栅栅介质二氧化铪的长度进行了优化。仿真结果表明:新型AG-TFET具有良好的电学特性,在室温下开关电流比可以达到3.3×1010,开态电流为302μA/μm,陡峭的亚阈值摆幅即点亚阈值摆幅为35 m V/dec,平均亚阈值摆幅为54 m V/dec。因此,该新型AG-TFET有望被应用在未来低功耗电路中。
文摘In this study,we fabricate Si/SiGe core-shell Junctionless accumulation mode(JAM)FinFET devices through a rapid and novel process with four main steps,i.e.e-beam lithography definition,sputter deposition,alloy combination annealing,and chemical solution etching.The height of Si core is 30 nm and the thickness of Si/SiGe core-shell is about 2 nm.After finishing the fabrication of devices,we widely studied the electrical characteristics of poly Si/SiGe core-shell JAM FinFET transistors from a view of different Lg and Wch.A poly-Si/SiGe core-shell JAMFETs was successfully demonstrated and it also exhibits a superior subthreshold swing of 81mV/dec and high on/off ratio>10^5 when annealing for 1hr at 600℃.The thermal diffusion process condition for this study are 1hr at 600℃ and 6hr at 700℃ for comparison.The annealing condition at 700oC for 6 hours shows undesired electrical characteristics against the other.Results suggests that from over thermal budget causes a plenty of Ge to precipitate against to form SiGe thin film.Annealing JAMFETs at low temperature shows outstanding Subthreshold swing and better swing condition when compared to its counterpart i.e.at higher temperature.This new process can still fabricate a comparable performance to classical planar FinFET in driving current.
