Combined effects of cycling endurance and total ionizing dose on floating gate memory cells

The combined effects of cycling endurance and radiation on floating gate memory cell are investigated in detail,and the obtained results are listed below.(i)The programmed flash cells with a prior appropriate number of program and easing cycling stress exhibit much smaller threshold voltage shift than without those in response to radiation,which is ascribed mainly to the recombination of trapped electrons(introduced by cycling stress)and trapped holes(introduced by irradiation)in the oxide surrounding the floating gate.(ii)The radiation induced transconductance degradation in prior cycled flash cell is more severe than those without cycling stress in the programmed state or erased state.(iii)Radiation is more likely to set up the interface generation in programmed state than in erased state.This paper will be useful in understanding the issues involved in cycling endurance and radiation effects as well as in designing radiation hardened floating gate memory cells.

Numerical simulation study of organic nonvolatile memory with polysilicon floating gate

A polysilicon-based organic nonvolatile floating-gate memory device with a bottom-gate top-contact configuration is investigated,in which polysilicon is sandwiched between oxide layers as a floating gate.Simulations for the electrical characteristics of the polysilicon floating gate-based memory device are performed.The shifted transfer characteristics and corresponding charge trapping mechanisms during programing and erasing（P/E） operations at various P/E voltages are discussed.The simulated results show that present memory exhibits a large memory window of 57.5 V,and a high read current on/off ratio of ≈ 10~3.Compared with the reported experimental results,these simulated results indicate that the polysilicon floating gate based memory device demonstrates remarkable memory effects,which shows great promise in device designing and practical application.

Effects of post-annealed floating gate on the performance of AlGaN/GaN heterostructure field-effect transistors

AlGaN/GaN heterostructure field-effect transistors （HFETs） with different floating gate lengths and floating gates annealed at different temperatures, are fabricated. Using the measured capacitance-voltage curves of the gate Shottky contacts for the AlGaN/GaN HFETs, we find that after floating gate experiences 600℃ rapid thermal annealing, the larger the floating gate length, the larger the two-dimensional electron gas electron density under the gate region is. Based on the measured capacitance-voltage and current-voltage curves, the strain of the AlGaN barrier layer in the gate region is calculated, which proves that the increased electron density originates from the increased strain of the AlGaN barrier layer.

STUDIES ON PROGRAMMING FEATURES AND METHODS OF FLOATING GATE MOSFET AS ANALOG MEMORY FOR SYNAPTIC WEIGHTS IN NEURAL NETWORKS

The features of the floating gate devices as analog memory have been investigatedexperimentally.Programming properties of the devices,compatibility and endurance of program-ming,and programming methods are presented in this paper.The results illustrate that thedevice can be used to store the analog weights for the neural networks,and the method that thestored value is adjusted continuously to approach to a given analog values is a rather practicalmethod for storing weights of neural networks.

A novel enhancement mode AlGaN/GaN high electron mobility transistor with split floating gates

A novel enhancement-mode AlGaN/GaN high electron mobility transistor（HEMT） is proposed and studied.Specifically,several split floating gates（FGs） with negative charges are inserted to the conventional MIS structure.The simulation results revealed that the V_（th） decreases with the increase of polarization sheet charge density and the tunnel dielectric（between FGs and AlGaN） thickness,while it increases with the increase of FGs sheet charge density and blocking dielectric（between FGs and control gate） thickness.In the case of the same gate length,the V_（th） will left shift with decreasing FG length.More interestingly,the split FGs could significantly reduce the device failure probability in comparison with the single large area FG structure.

Designing a Full Adder Circuit Based on Quasi-Floating Gate

Since in designing the full adder circuits, full adders have been generally taken into account, so as in this paper it has been attempted to represent a full adder cell with a significant efficiency of power, speed and leakage current levels. For this objective, a comparison between five full adder circuits has been provided. Applying floating gate technology and refresh circuits in the full adder cell lead to the reduction of leakage current on the gate node. The simulations were accomplished in this paper, through HSPICE software and 65 nm CMOS technology. The simulation results indicate the considerable efficiency of power consumption, speed and leakage current in the full adder cell rather than other cells.

Organic field-effect transistor floating-gate memory using polysilicon as charge trapping layer

In this study,we present an organic field-effect transistor floating-gate memory using polysilicon(poly-Si)as a charge trapping layer.The memory device is fabricated on a N^+-Si/SiO2 substrate.Poly-Si,polymethylmethacrylate,and pentacene are used as a floating-gate layer,tunneling layer,and active layer,respectively.The device shows bidirectional storage characteristics under the action of programming/erasing(P/E)operation due to the supplied electrons and holes in the channel and the bidirectional charge trapping characteristic of the poly-Si floating-gate.The carrier mobility and switching current ratio(Ion/Ioff ratio)of the device with a tunneling layer thickness of 85 nm are 0.01 cm^2·V^-1·s^-1 and 102,respectively.A large memory window of 9.28 V can be obtained under a P/E voltage of±60 V.

Design,modelling,and simulation of a floating gate transistor with a novel security feature

This study proposes a new generation of floating gate transistors(FGT)with a novel built-in security feature.The new device has applications in guarding the IC chips against the current reverse engineering techniques,including scanning capacitance microscopy(SCM).The SCM measures the change in the C–V characteristic of the device as a result of placing a minute amount of charge on the floating gate,even in nano-meter scales.The proposed design only adds a simple processing step to the conventional FGT by adding an oppositely doped implanted layer to the substrate.This new structure was first analyzed theoretically and then a two-dimensional model was extracted to represent its C–V characteristic.Furthermore,this model was verified with a simulation.In addition,the C–V characteristics relevant to the SCM measurement of both conventional and the new designed FGT were compared to discuss the effectiveness of the added layer in masking the state of the transistor.The effect of change in doping concentration of the implanted layer on the C–V characteristics was also investigated.Finally,the feasibility of the proposed design was examined by comparing its I–V characteristics with the traditional FGT.

Decisive Parameters for Backwater Effects Caused by Floating Debris Jams

The dimensional analysis of the backwater effect caused by debris jams results in the Froude number of the approach flow in the initial situation prior to debris jam formation and the debris density as decisive parameters. For the more precise detection of the influence of both parameters the results of different hydraulic model test series at the Laboratory of Hydraulic and Water Resources Engineering of the Technical University of Munich concerning debris jams at spillways as well as at racks for the retention of wooden debris were uniformly evaluated. On the one hand a significant increase of the backwater effect with a rising Froude number of the approach flow could be shown. This is in good correlation to recent test results for debris jams at retention racks at the Laboratory of Hydraulics, Hydrology and Glaciology of the Swiss Federal Institute of Technology Zurich. On the other hand a significant increase of the backwater effect could also be shown for a rising debris density. However, the test results also show that significantly different backwater effects can occur in different test runs with identical test conditions. These differences are a result of the randomness of debris jam development, and therefore, a more exact quantification of the dependence of the backwater effect on the Froude number of the approach flow and on the debris density is not considered useful for the present results.

基于FPGA误差可控的浮点运算加速器研究

浮点运算是高性能计算(HPC)领域的基础运算。在大数据与云计算的背景下,高性能计算平台需要处理的数据量与日俱增,而且浮点数的舍入误差在大规模、长时程的运算中会产生累积,因此,在提升浮点运算性能的同时保证计算结果的可靠性非常重要。利用现场可编程门阵列(FPGA)可编程、低功耗、灵活性强的特点,针对含复杂单项运算的浮点多项式设计一种浮点运算加速器。基于无误差变换的思想,通过计算得出舍入误差值,将其补偿到浮点数值上,从而实现误差可控。采用异步并行的方式实现运算加速,并通过构建CPU-FPGA平台最大化地利用计算资源,保证计算任务执行的高效性。数据测试结果表明:在不限制对称性下的数值相对论模拟运算中,该加速器在200 MHz的主频下可达到91.85 MFLOPs的峰值性能;与Intel i76700K CPU运行最大线程数的性能相比,该加速器实现了50.54的加速比,并在该条件下获得了平均53.6%的精确结果百分比以及更低的相对误差,表明其具备较高的可靠性。

具有多晶阻挡层的浮空P区IGBT开关特性研究

为了减少浮空P区IGBT结构的栅极空穴积累,改善结构的电磁干扰(EMI)噪声问题,从而提高结构电磁干扰噪声与开启损耗(Eon)之间的折中关系,研究提出了一种具有多晶硅阻挡层的FD-IGBT结构。新结构在传统结构的浮空P区上方引入一块多晶硅阻挡层,阻挡层接栅极,形成与N型漂移区的电势差。新结构在器件开启过程中,多晶硅阻挡层下方会积累空穴,导致栅极附近积累的空穴数量减少,从而降低浮空P区对栅极的反向充电电流。通过TCAD软件仿真结果表明,相比于传统FD-IGBT,新结构开启瞬态的过冲电流(I_(CE))和过冲电压(V_(GE))的峰值分别下降26.5%和8.6%,且在栅极电阻(R_(g))增加时有更好的电流电压可控性;相同开启损耗下,新结构的dI_(CE)/dt、dV_(CE)/dt和dV_(KA)/dt最大值分别降低26.5%,15.1%和26.1%。

Van der Waals materials-based floating gate memory for neuromorphic computing

With the advent of the“Big Data Era”,improving data storage density and computation speed has become more and more urgent due to the rapid growth in different types of data.Flash memory with a floating gate(FG)structure is attracting great attention owing to its advantages of miniaturization,low power consumption and reli-able data storage,which is very effective in solving the problems of large data capacity and high integration density.Meanwhile,the FG memory with charge storage principle can simulate synaptic plasticity perfectly,breaking the traditional von Neumann computing ar-chitecture and can be used as an artificial synapse for neuromorphic computations inspired by the human brain.Among many candidate materials for manufacturing devices,van der Waals(vdW)materials have attracted widespread attention due to their atomic thickness,high mobility,and sustainable miniaturization properties.Owing to the arbitrary stacking ability,vdW heterostructure combines rich physics and potential 3D integration,opening up various possibilities for new functional integrated devices with low power consumption and flexible applications.This paper provides a comprehensive review of memory devices based on vdW materials with FG structure,including the working principles and typical structures of FG structure devices,with a focus on the introduction of various highperformance FG memories and their versatile applications in neuro-morphic computing.Finally,the challenges of neuromorphic devices based on FG structures are also discussed.This review will shed light on the design and fabrication of vdW material-based memory devices with FG engineering,helping to promote the development of practical and promising neuromorphic computing.

浮栅和高压栅极共掺在EEPROM中的应用研究

为简化电可擦除可编程只读存储器(Electrically-erasable programmable read-only memory, EEPROM)的制造工艺以及减少等离子体对隧道氧化层的损害,重点分析了将浮栅多晶硅和高压器件的栅极共同掺杂对存储器件和高压器件的影响,包括不同掺杂浓度下EEPROM存储单元的擦写速度、读取电流、可靠性以及高压晶体管的电学特性等相关分析,探讨优良器件特性的最优掺杂浓度设计方法,为器件性能优化以及工艺改进提供参考。

大连湾海底隧道沉管预制干坞坞口设计与应用

大连湾海底隧道采用沉管法建设,由固定干坞承担18节沉管预制。坞口作为干坞与大海之间的屏障,在挡水防浪保障坞内安全方面至关重要,在安全、经济的前提下尚需兼顾施工便捷和使用方便。在总结国内外典型沉管预制场坞口形式的基础上,采用固定干坞法、重力式坞口、大沉箱浮坞门方案,坞口采用帷幕灌浆+止水带+钢闸门+混凝土结构止水体系,设有消能式自流灌水坞门墩结构,浮坞门沉箱采用原位现浇方案,可为类似工程提供参考。

浮体闸门翻转计算与结构分析

提出将浮体闸门充水过程中的旋转下沉运动拆解为下沉和旋转两个独立运动,通过解析法推导出了传统等截面浮体检修闸门充水过程中旋转中心的计算公式;基于旋转中心的计算公式,分析等截面浮体闸门和变截面浮体闸门的翻转过程,并对其吃水深度、所需配重及稳定性进行对比分析,得出变截面浮体闸门结合门底配重的结构形式在翻转过程中稳定性更高且对水深的要求更低。

Impact of back-gate bias on the hysteresis effect in partially depleted SOI MOSFETs

The hysteresis effect in the output characteristics,originating from the floating body effect,has been measured in partially depleted（PD） silicon-on-insulator（SOI） MOSFETs at different back-gate biases.I D hysteresis has been developed to clarify the hysteresis characteristics.The fabricated devices show the positive and negative peaks in the I D hysteresis.The experimental results show that the I D hysteresis is sensitive to the back gate bias in 0.13-渭m PD SOI MOSFETs and does not vary monotonously with the back-gate bias.Based on the steady-state Shockley-Read-Hall（SRH） recombination theory,we have successfully interpreted the impact of the back-gate bias on the hysteresis effect in PD SOI MOSFETs.

Gate-to-body tunneling current model for silicon-on-insulator MOSFETs

A gate-to-body tunneling current model for silicon-on-insulator （SOl） devices is simulated. As verified by the mea- sured data, the model, considering both gate voltage and drain voltage dependence as well as image force-induced barrier low effect, provides a better prediction of the tunneling current and gate-induced floating body effect than the BSIMSOI4 model. A delayed gate-induced floating body effect is also predicted by the model.

Realization of an 850V High Voltage Half Bridge Gate Drive IC with a New NFFP HVI Structure

A NFFP HVI structure which implements high breakdown voltage without using additional FFP and process steps is proposed in this paper. An 850 V high voltage half bridge gate drive IC with the NFFP HVI structure is experimentally realized using a thin epitaxial BCD process. Compared with the MFFP HVI structure, the proposed NFFP HVI structure shows simpler process and lower cost. The high side offset voltage in the half bridge gate drive IC with the NFFP HVI structure is almost as same as that with the self-shielding structure.

NP-Domino, Ultra-Low-Voltage, High-Speed, Dual-Rail, CMOS NOR Gates

In this paper, novel ultra low voltage (ULV) dual-rail NOR gates are presented which use the semi-floating-gate (SFG) structure to speed up the logic circuit. Higher speed in the lower supply voltages and robustness against the input signal delay variations are the main advantages of the proposed gates in comparison to the previously reported domino dual-rail NOR gates. The simulation results in a typical TSMC 90 nm CMOS technology show that the proposed NOR gate is more than 20 times faster than conventional dual-rail NOR gate.

一种昼夜兼容成像EMCCD图像传感器

本文设计制作了一款阵列规模为1024×1024元、像元尺寸为10μm×10μm的昼夜兼容成像EMCCD(electron multiplying charge coupled device),该器件包含国内首次制作的浮置栅放大器,该放大器电荷转换因子(Charge to voltage factor,CVF)为3.57μV/e^(-),满阱55 ke^(-),能够非破坏性判断信号强度。该功能使得场景中微光照区域的像素可以选择性地路由至倍增通道输出,而强光照区域的像素会路由至非倍增通道输出,有了这种场景内可切换增益特性,两种输出的信号重新组合,实现高动态成像。同时为了实现器件在强光应用场合的抗光晕功能,器件像元区域采用了纵向抗晕设计,抗晕倍数为200倍,基于此类器件制作的相机能够恰当地在暗视场中呈现明亮的图像。