By using the pulsed laser single event effect facility and electro-static discharge （ESD） test system, the characteristics of the ＂high current＂, relation with external stimulus and relevance to impacted modes of ...By using the pulsed laser single event effect facility and electro-static discharge （ESD） test system, the characteristics of the ＂high current＂, relation with external stimulus and relevance to impacted modes of single event latch-up （SEL） and transient-induced latch-up （TLU） are studied, respectively, for a 12-bit complementary metal--oxide semiconductor （CMOS） analog-to-digital converter. Furthermore, the sameness and difference in physical mechanism between ＂high current＂ induced by SEL and that by TLU are disclosed in this paper. The results show that the minority carrier diffusion in the PNPN structure of the CMOS device which initiates the active parasitic NPN and PNP transistors is the common reason for the ＂high current＂ induced by SEL and for that by TLU, However, for SEL, the minority carder diffusion is induced by the ionizing radiation, and an underdamped sinusoidal voltage on the supply node （the ground node） is the cause of the minority carrier diffusion for TLU.展开更多
The latch-up effect induced by high-power microwave（HPM） in complementary metal–oxide–semiconductor（CMOS） inverter is investigated in simulation and theory in this paper. The physical mechanisms of excess carrie...The latch-up effect induced by high-power microwave（HPM） in complementary metal–oxide–semiconductor（CMOS） inverter is investigated in simulation and theory in this paper. The physical mechanisms of excess carrier injection and HPM-induced latch-up are proposed. Analysis on upset characteristic under pulsed wave reveals increasing susceptibility under shorter-width pulsed wave which satisfies experimental data, and the dependence of upset threshold on pulse repetitive frequency（PRF） is believed to be due to the accumulation of excess carriers. Moreover, the trend that HPMinduced latch-up is more likely to happen in shallow-well device is proposed.Finally, the process of self-recovery which is ever-reported in experiment with its correlation with supply voltage and power level is elaborated, and the conclusions are consistent with reported experimental results.展开更多
Considering the phenomenon of Latch-up in CMOS device,some patterns of manifestation about Latch-up in electronic system are analyzed with three actual circuits,meanwhile the correlative solving methods are also provi...Considering the phenomenon of Latch-up in CMOS device,some patterns of manifestation about Latch-up in electronic system are analyzed with three actual circuits,meanwhile the correlative solving methods are also provided. To avoid Latch-up,some general principles are proposed. The analyzing and solving processes derived from practical system design are verified simple and ef-fective in large number of products,and to some extend have general reference value in anti-latch-up design of application systems.展开更多
An improved on-chip CMOS astable multivibrator is proposed, which overcomes the shortcomings of the traditional one that the signal duty-cycle is depending on model parameters, and generates stable clock signal with d...An improved on-chip CMOS astable multivibrator is proposed, which overcomes the shortcomings of the traditional one that the signal duty-cycle is depending on model parameters, and generates stable clock signal with duty-cycle equaling 50%. The latch-up effect has been prevented on the improved circuit. It is extremely important that all the excellent performances of the improved astable multivibrator have been achieved with a dynamic power consumption equaling its predecessor one. The advantage of the structure has been verified by SPICE simulation.展开更多
A novel substrate trigger semiconductor control rectifier-laterally diffused metal-oxide semiconductor （STSCR- LDMOS） stacked structure is proposed and simulated using the transimission line pulser （TLP） multiple-...A novel substrate trigger semiconductor control rectifier-laterally diffused metal-oxide semiconductor （STSCR- LDMOS） stacked structure is proposed and simulated using the transimission line pulser （TLP） multiple-pulse simulation method in a 0.35μm, 60-V biploar-CMOS-DMOS （BCD） process without additional masks. On account of a very low holding voltage, it is susceptible to latch-up-like danger for the semiconductor control rectifier-laterally diffused metaloxide semiconductor （SCR-LDMOS） in high-voltage electro-static discharge （ESD） protection applications. Although the conventional stacking structure has achieved strong latch-up immunity by increasing holding voltage, excessive high trigger voltage does not meet requirements for an ESD protection device. The holding voltage of the proposed stacked structure is proportional to the stacking number, whereas the trigger voltage remains nearly the same. A high holding voltage of 30.6 V and trigger voltage of 75.4 V are achieved.展开更多
Cooperation between manufacturing and other functional groups is critical to improve the success of new products. However, integrating operations and development methodologies is often challenging due to conflicting p...Cooperation between manufacturing and other functional groups is critical to improve the success of new products. However, integrating operations and development methodologies is often challenging due to conflicting priorities and organizational structures. Improving the quality of product development and the transition to manufacturing is not a new venture. Organizations have been incorporating planning and continuous improvement to their product develop-ment initiatives for decades. This paper summarizes the experience of I/O libraries quality certification within Freescale Semiconductor and describes the certification flow developed by Corporate Quality and I/O Design teams.展开更多
The low snapback holding voltage of the SCR-LDMOS device makes it susceptible to latch-up failure,when used in power-rail ESD（electro-static discharge） clamp circuits.In order to eliminate latch-up risk,this work pr...The low snapback holding voltage of the SCR-LDMOS device makes it susceptible to latch-up failure,when used in power-rail ESD（electro-static discharge） clamp circuits.In order to eliminate latch-up risk,this work presents a novel SCR-LDMOS structure with an N-type implantation layer to achieve a 17 V holding voltage and a 5.2 A second breakdown current.The device has been validated using TLP measurement analysis and is applied to a power-rail ESD clamp in half-bridge driver ICs.展开更多
The temperature dependence of the latch-up effects in a CMOS inverter based on 0.5 μm technology caused by high power microwave （HPM） is studied. The malfunction and power supply current characteristics are reveale...The temperature dependence of the latch-up effects in a CMOS inverter based on 0.5 μm technology caused by high power microwave （HPM） is studied. The malfunction and power supply current characteristics are revealed and adopted as the latch-up criteria. The thermal effect is shown and analyzed in detail. CMOS in- verters operating at high ambient temperature are confirmed to be more susceptible to HPM, which is verified by experimental results from previous literature. Besides the dependence of the latch-up triggering power P on the ambient temperature T follows the power-law equation P = ATβ. Meanwhile, the ever reported latch-up delay time characteristic is interpreted to be affected by the temperature distribution. In addition, it is found that the power threshold increases with the decrease in pulse width but the degree of change with a certain pulse width is constant at different ambient temperatures. Also, the energy absorbed to cause latch-up at a certain temperature is basically sustained at a constant value.展开更多
An improved trench gate super-junction insulated-gate bipolar transistor is presented. The improved structure contains two emitter regions. The first emitter region of the device works as the conventional structure,wh...An improved trench gate super-junction insulated-gate bipolar transistor is presented. The improved structure contains two emitter regions. The first emitter region of the device works as the conventional structure,which can absorb both the electron current and hole current. The second emitter on the top of the p-pillar acts as the hole current diverter, leading to an improved latch-up capability without sacrificing the off-state breakdown voltage（BV） and turn-off loss. The simulation shows that the latch-up limit of the SJ-IGBT increases from 15000 to 28300 A/cm^2 at VGE D10 V, the BV is 810 V, and the turn off loss is 6.5 m J/cm^2 at Von D1.2 V.展开更多
基金Project supported by the National Natural Science Foundation of China(Grant No.41304148)
文摘By using the pulsed laser single event effect facility and electro-static discharge （ESD） test system, the characteristics of the ＂high current＂, relation with external stimulus and relevance to impacted modes of single event latch-up （SEL） and transient-induced latch-up （TLU） are studied, respectively, for a 12-bit complementary metal--oxide semiconductor （CMOS） analog-to-digital converter. Furthermore, the sameness and difference in physical mechanism between ＂high current＂ induced by SEL and that by TLU are disclosed in this paper. The results show that the minority carrier diffusion in the PNPN structure of the CMOS device which initiates the active parasitic NPN and PNP transistors is the common reason for the ＂high current＂ induced by SEL and for that by TLU, However, for SEL, the minority carder diffusion is induced by the ionizing radiation, and an underdamped sinusoidal voltage on the supply node （the ground node） is the cause of the minority carrier diffusion for TLU.
基金Project supported by the Open Fund of Key Laboratory of Complex Electromagnetic Environment Science and Technology,China Academy of Engineering Physics(Grant No.2015-0214.XY.K)
文摘The latch-up effect induced by high-power microwave（HPM） in complementary metal–oxide–semiconductor（CMOS） inverter is investigated in simulation and theory in this paper. The physical mechanisms of excess carrier injection and HPM-induced latch-up are proposed. Analysis on upset characteristic under pulsed wave reveals increasing susceptibility under shorter-width pulsed wave which satisfies experimental data, and the dependence of upset threshold on pulse repetitive frequency（PRF） is believed to be due to the accumulation of excess carriers. Moreover, the trend that HPMinduced latch-up is more likely to happen in shallow-well device is proposed.Finally, the process of self-recovery which is ever-reported in experiment with its correlation with supply voltage and power level is elaborated, and the conclusions are consistent with reported experimental results.
基金Scientific Research Fund of Zhejiang Provincial Education Department. Project name:Research and Design on Network Communication Controller for Fiber Cable TV.Project number:20061473.
文摘Considering the phenomenon of Latch-up in CMOS device,some patterns of manifestation about Latch-up in electronic system are analyzed with three actual circuits,meanwhile the correlative solving methods are also provided. To avoid Latch-up,some general principles are proposed. The analyzing and solving processes derived from practical system design are verified simple and ef-fective in large number of products,and to some extend have general reference value in anti-latch-up design of application systems.
文摘An improved on-chip CMOS astable multivibrator is proposed, which overcomes the shortcomings of the traditional one that the signal duty-cycle is depending on model parameters, and generates stable clock signal with duty-cycle equaling 50%. The latch-up effect has been prevented on the improved circuit. It is extremely important that all the excellent performances of the improved astable multivibrator have been achieved with a dynamic power consumption equaling its predecessor one. The advantage of the structure has been verified by SPICE simulation.
文摘A novel substrate trigger semiconductor control rectifier-laterally diffused metal-oxide semiconductor （STSCR- LDMOS） stacked structure is proposed and simulated using the transimission line pulser （TLP） multiple-pulse simulation method in a 0.35μm, 60-V biploar-CMOS-DMOS （BCD） process without additional masks. On account of a very low holding voltage, it is susceptible to latch-up-like danger for the semiconductor control rectifier-laterally diffused metaloxide semiconductor （SCR-LDMOS） in high-voltage electro-static discharge （ESD） protection applications. Although the conventional stacking structure has achieved strong latch-up immunity by increasing holding voltage, excessive high trigger voltage does not meet requirements for an ESD protection device. The holding voltage of the proposed stacked structure is proportional to the stacking number, whereas the trigger voltage remains nearly the same. A high holding voltage of 30.6 V and trigger voltage of 75.4 V are achieved.
文摘Cooperation between manufacturing and other functional groups is critical to improve the success of new products. However, integrating operations and development methodologies is often challenging due to conflicting priorities and organizational structures. Improving the quality of product development and the transition to manufacturing is not a new venture. Organizations have been incorporating planning and continuous improvement to their product develop-ment initiatives for decades. This paper summarizes the experience of I/O libraries quality certification within Freescale Semiconductor and describes the certification flow developed by Corporate Quality and I/O Design teams.
基金Project supported by the Natural Science Foundation of Jiangsu Province (No.BK2011059)the Program for New Century Excellent Talent in University (No.NCET-10-0331)
文摘The low snapback holding voltage of the SCR-LDMOS device makes it susceptible to latch-up failure,when used in power-rail ESD（electro-static discharge） clamp circuits.In order to eliminate latch-up risk,this work presents a novel SCR-LDMOS structure with an N-type implantation layer to achieve a 17 V holding voltage and a 5.2 A second breakdown current.The device has been validated using TLP measurement analysis and is applied to a power-rail ESD clamp in half-bridge driver ICs.
基金Project supported by the National Natural Science Foundation of China(No.60776034)the State Key Development Program for Basic Research of China(No.2014CC339900)
文摘The temperature dependence of the latch-up effects in a CMOS inverter based on 0.5 μm technology caused by high power microwave （HPM） is studied. The malfunction and power supply current characteristics are revealed and adopted as the latch-up criteria. The thermal effect is shown and analyzed in detail. CMOS in- verters operating at high ambient temperature are confirmed to be more susceptible to HPM, which is verified by experimental results from previous literature. Besides the dependence of the latch-up triggering power P on the ambient temperature T follows the power-law equation P = ATβ. Meanwhile, the ever reported latch-up delay time characteristic is interpreted to be affected by the temperature distribution. In addition, it is found that the power threshold increases with the decrease in pulse width but the degree of change with a certain pulse width is constant at different ambient temperatures. Also, the energy absorbed to cause latch-up at a certain temperature is basically sustained at a constant value.
基金Project supported by the National Natural Science Foundation of China(No.61204083)the Natural Science Foundation of the Jiangsu Province of China(Nos.BK2012204,BY2011146)the Scientific Research Guidance Foundation of Southeast University Wuxi Branch Campus
文摘An improved trench gate super-junction insulated-gate bipolar transistor is presented. The improved structure contains two emitter regions. The first emitter region of the device works as the conventional structure,which can absorb both the electron current and hole current. The second emitter on the top of the p-pillar acts as the hole current diverter, leading to an improved latch-up capability without sacrificing the off-state breakdown voltage（BV） and turn-off loss. The simulation shows that the latch-up limit of the SJ-IGBT increases from 15000 to 28300 A/cm^2 at VGE D10 V, the BV is 810 V, and the turn off loss is 6.5 m J/cm^2 at Von D1.2 V.
