We present an overview of approaches to selfvalidating?one-dimensional integration quadrature formulas and?a verified numerical integration algorithm with an adaptive?strategy. The new interval integration adaptive al...We present an overview of approaches to selfvalidating?one-dimensional integration quadrature formulas and?a verified numerical integration algorithm with an adaptive?strategy. The new interval integration adaptive algorithm delivers?a desired integral enclosure with an error bounded by a specified?error bound. The adaptive technique is usually much more?efficient than Simpson’s rule and narrow interval results can?be reached.展开更多
As an efficient artificial truncating boundary condition, conformal perfectly matched layer (CPML) is a kind of multilayer anisotropic absorbing media. To reduce computing effort of CPML, this article proposes a layer...As an efficient artificial truncating boundary condition, conformal perfectly matched layer (CPML) is a kind of multilayer anisotropic absorbing media. To reduce computing effort of CPML, this article proposes a layer-oriented element integration algorithm. In this algorithm, the relative dielectric constant and permeability are considered as constants for each the very thin monolayer of CPML, and the element integration of multilayer along the normal direction is substituted by the element integration of m...展开更多
The paper brings an important integral inequality, which includes the famous Polya-Szego inequality and the logarithmical-arithmetic mean inequality as special cases.
Two optimization technologies, namely, bypass and carry-control optimization, were demonstrated for enhancing the performance of a bit-slice Arithmetic Logic Unit (ALU) in 2n-bit Rapid Single-Flux-Quantum (RSFQ) micro...Two optimization technologies, namely, bypass and carry-control optimization, were demonstrated for enhancing the performance of a bit-slice Arithmetic Logic Unit (ALU) in 2n-bit Rapid Single-Flux-Quantum (RSFQ) microprocessors. These technologies can not only shorten the calculation time but also solve data hazards. Among them, the proposed bypass technology is applicable to any 2n-bit ALU, whether it is bit-serial, bit-slice or bit-parallel. The high performance bit-slice ALU was implemented using the 6 kA/cm^(2) Nb/AlOx/Nb junction fabrication process from Superconducting Electronics Facility of Shanghai Institute of Microsystem and Information Technology. It consists of 1693 Josephson junctions with an area of 2.46 0.81 mm^(2). All ALU operations of the MIPS32 instruction set are implemented, including two extended instructions, i.e., addition with carry (ADDC) and subtraction with borrow (SUBB). All the ALU operations were successfully obtained in SFQ testing based on OCTOPUX and the measured DC bias current margin can reach 86% - 104%. The ALU achieves a 100 utilization rate, regardless of carry/borrow read-after-write correlations between instructions.展开更多
文摘We present an overview of approaches to selfvalidating?one-dimensional integration quadrature formulas and?a verified numerical integration algorithm with an adaptive?strategy. The new interval integration adaptive algorithm delivers?a desired integral enclosure with an error bounded by a specified?error bound. The adaptive technique is usually much more?efficient than Simpson’s rule and narrow interval results can?be reached.
基金National Natural Science Foundation of China (10477018) Science and Technology Innovation Foundation of North-western Polytechnical University (W016143)
文摘As an efficient artificial truncating boundary condition, conformal perfectly matched layer (CPML) is a kind of multilayer anisotropic absorbing media. To reduce computing effort of CPML, this article proposes a layer-oriented element integration algorithm. In this algorithm, the relative dielectric constant and permeability are considered as constants for each the very thin monolayer of CPML, and the element integration of multilayer along the normal direction is substituted by the element integration of m...
基金the Scientific Research fund of Pingyuan University(2005006)
文摘The paper brings an important integral inequality, which includes the famous Polya-Szego inequality and the logarithmical-arithmetic mean inequality as special cases.
基金Strategic Priority Research Program of Chinese Academy of Sciences,under Grant XDA18000000.
文摘Two optimization technologies, namely, bypass and carry-control optimization, were demonstrated for enhancing the performance of a bit-slice Arithmetic Logic Unit (ALU) in 2n-bit Rapid Single-Flux-Quantum (RSFQ) microprocessors. These technologies can not only shorten the calculation time but also solve data hazards. Among them, the proposed bypass technology is applicable to any 2n-bit ALU, whether it is bit-serial, bit-slice or bit-parallel. The high performance bit-slice ALU was implemented using the 6 kA/cm^(2) Nb/AlOx/Nb junction fabrication process from Superconducting Electronics Facility of Shanghai Institute of Microsystem and Information Technology. It consists of 1693 Josephson junctions with an area of 2.46 0.81 mm^(2). All ALU operations of the MIPS32 instruction set are implemented, including two extended instructions, i.e., addition with carry (ADDC) and subtraction with borrow (SUBB). All the ALU operations were successfully obtained in SFQ testing based on OCTOPUX and the measured DC bias current margin can reach 86% - 104%. The ALU achieves a 100 utilization rate, regardless of carry/borrow read-after-write correlations between instructions.
