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Device performance limit of monolayer SnSe_(2) MOSFET 被引量:1
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作者 Hong Li Jiakun Liang +5 位作者 Qida Wang Fengbin Liu Gang Zhou Tao Qing Shaohua Zhang Jing Lu 《Nano Research》 SCIE EI CSCD 2022年第3期2522-2530,共9页
Two-dimensional(2D)semiconductors are attractive channels to shrink the scale of field-effect transistors(FETs),and among which the anisotropic one is more advantageous for a higher on-state current(I_(on)).Monolayer(... Two-dimensional(2D)semiconductors are attractive channels to shrink the scale of field-effect transistors(FETs),and among which the anisotropic one is more advantageous for a higher on-state current(I_(on)).Monolayer(ML)SnSe_(2),as an abundant,economic,nontoxic,and stable two-dimensional material,possesses an anisotropic electronic nature.Herein,we study the device performances of the ML SnSe_(2) metal-oxide-semiconductor FETs(MOSFETs)and deduce their performance limit to an ultrashort gate length(L_(g))and ultralow supply voltage(V_(dd))by using the ab initio quantum transport simulation.An ultrahigh I_(on) of 5,660 and 3,145µA/µm is acquired for the n-type 10-nm-L_(g) ML SnSe_(2) MOSFET at V_(dd)=0.7 V for high-performance(HP)and low-power(LP)applications,respectively.Specifically,until L_(g) scales down to 2 and 3 nm,the MOSFETs(at V_(dd)=0.65 V)surpass I_(on),intrinsic delay time(τ),and power-delay product(PDP)of the International Roadmap for Device and Systems(IRDS,2020 version)for HP and LP devices for the year 2028.Moreover,the 5-nm-L_(g) ML SnSe_(2) MOSFET(at V_(dd)=0.4 V)fulfills the IRDS HP device and the 7-nm-L_(g) MOSFET(at V_(dd)=0.55 V)fulfills the IRDS LP device for the year 2034. 展开更多
关键词 monolayer(ML)SnSe_(2) ANISOTROPIC metal-oxide-semiconductor field-effect transistor(MOSFET) device performance limit ab initio transport simulation
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Concept and design of super junction devices 被引量:4
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作者 Bo Zhang Wentong Zhang +2 位作者 Ming Qiao Zhenya Zhan Zhaoji Li 《Journal of Semiconductors》 EI CAS CSCD 2018年第2期1-12,共12页
The super junction(SJ) has been recognized as the "milestone" of the power MOSFET, which is the most important innovation concept of the voltage-sustaining layer(VSL). The basic structure of the SJ is a typical ... The super junction(SJ) has been recognized as the "milestone" of the power MOSFET, which is the most important innovation concept of the voltage-sustaining layer(VSL). The basic structure of the SJ is a typical junction-type VSL(J-VSL) with the periodic N and P regions. However, the conventional VSL is a typical resistance-type VSL(R-VSL) with only an N or P region. It is a qualitative change of the VSL from the R-VSL to the JVSL, introducing the bulk depletion to increase the doping concentration and optimize the bulk electric field of the SJ. This paper firstly summarizes the development of the SJ, and then the optimization theory of the SJ is discussed for both the vertical and the lateral devices, including the non-full depletion mode, the minimum specific on-resistance optimization method and the equivalent substrate model. The SJ concept breaks the conventional"silicon limit" relationship of R_(on)∝V_B^(2.5), showing a quasi-linear relationship of R_(on)∝V_B^(1.03). 展开更多
关键词 super junction silicon limit power semiconductor device design theory
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