Analysis of the Design Methods of Word Oriented Linear Feedback Shift Registers

Based on analysis of the structure characteristics and implementation methods of some representative word oriented linear feedback shift registers （LFSRs） in several modem software oriented stream ciphers, this paper firstly classifies the word oriented LFSRs into two classes： the machine instruction type and the arithmetic type. The similarities and differences between each type are illustrated by concrete examples. Then we give a detailed analysis about the word oriented LFSRs in each category from design structure, cryptographic properties and implementation issue aspects. Finally, some basic design criteria for modem word oriented LFSRs and suitable for software implementation are summarized.

Blind reconstruction of linear scrambler

An algorithm based on eigenanalysis technique and Walsh-Hadamard transform （WriT） is proposed. The algorithm contains two steps. Firstly, the received sequence is divided into temporal windows, and a covariance matrix is computed. The linear feedback shift register （LFSR） sequence is reconstructed from the first eigenvector of this matrix. Secondly, equations according to the recovered LFSR sequence are constructed, and the Walsh spectrum corresponding to the equations is computed. The feedback polynomial of LFSR is estimated from the Walsh spectrum. The validity of the algorithm is verified by the simulation result. Finally, case studies are presented to illustrate the performance of the blind reconstruction method.

Algebraic attacks on two kinds of special nonlinear filter generators

This letter proposes algebraic attacks on two kinds of nonlinear filter generators with symmetric Boolean functions as the filter fimctions. Different fxom the classical algebraic attacks, the proposed attacks take the advantage of the combinational property of a linear feedback shift register （LFSR） and the symmetric Boolean function to obtain a tow-degree algebraic relation, and hence the complexities of the proposed attacks are independent of the algebraic immunity （AI） of the filter functions. It is shown that improper combining of the LFSR with the filter function can make the filter generator suffer from algebraic attacks. As a result, the bits of the LFSR must be selected properly to input the filter function with large AI in order to withstand the proposed algebraic attacks.

Finding Non-liner Register on Binary M-Sequence Generating Binary Multiplication Sequence

In the current time there is an important problem that is for a received linear or nonlinear binary sequence{z_(n)}how we can find the nonlinear feedback shift register and its linear equivalent which generate this sequence.The linear orthogonal sequences,special M-Sequences,play a big role in these methods for solving this problem.In the current research trying give illuminations about the methods which are very useful for solving this problem under short sequences,and study these methods for finding the nonlinear feedback shift register of a multiplication sequence and its linear equivalent feedback shift register of a received multiplication binary sequence{z_(n)}where the multiplication on h degrees of a binary linear sequence{a_(n)},or finding the equivalent linear feedback shift register of{z_(n)},where the sequence{z_(n)}of the form M-sequence,and these methods are very effectively.We can extend these methods for the large sequences using programming and modern computers with large memory.

Evolutionary Random Sequence Generators Based on LFSR

Random numbers play a crucial role in modern security schemes. Couple to the rapid development of cryptography, the strength of security protocols and encryption algorithms consumingly relies on the quality of random number. With simple architecture and faster speed, linear feedback shift register often is selected in many applications. However, the random sequence generated by LFSR can not meet the demand of unpredictability for secure mechanism. Genetic algorithm improves the linear property of LFSR and constructs a novel random sequence generator with longer period and complex architecture.

An efficient method for parallel CRC automatic generation

The State Transition Equation (STE) based method to automatically generate the parallel CRC circuits for any generator polynomial or required amount of parallelism is presented. The parallel CRC circuit so generated is partially optimized before being fed to synthesis tools and works properly in our LAN transceiv-er. Compared with the cascading method, the proposed method gives better timing results and significantly re-duces the synthesis time, in particular.

A vector inserting TPG for BIST design with low peak power consumption

A test pattern generator （TPG） which can highly reduce the peak power consumption during built-in self-test （BIST） application is proposed. The proposed TPG, called LPpe-TPG, consists of a linear feedback shift register （LFSR） and some control circuits. A procedure is presented firstly to make compare vectors between pseudorandom test patterns by adding some circuits to the original LFSR and secondly to insert some vectors between two successive pseudorandom test patterns according to the ordinal selection of every two bits of the compare vector. Then the changes between any successive test patterns of the test set generated by the LPpe-TPG are not more than twice. This leads to a decrease of the weighted switching activity （WSA） of the circuit under test （CUT） and therefore a reduction of the power consumption. Experimental results based on some ISCAS＇ 85 benchmark circuits show that the peak power consumption has been reduced by 25.25% to 64.46%. Also, the effectiveness of our approach to reduce the total and average power consumption is kept, without losing stuck-at fault coverage.

Ethernet Controller SoC Design and Its Low-Power DFT Considerations

In this paper, an Ethernet controller SoC solution and its low power design for testability （DFT） for information appliances are presented. On a single chip, an enhanced one-cycle 8-bit micro controller unit （MCU）, media access control （MAC） circuit and embedded memories such as static random access memory （SRAM）, read only memory （ROM） and flash are all integrated together. In order to achieve high fault coverage, at the same time with low test power, different DFT techniques are adopted for different circuits： the scan circuit that reduces switching activity is implemented for digital logic circuits; BIST-based method is employed for the on-chip SRAM and ROM. According to the fault-modeling of embedded flash, we resort to a March-like method for flash built in self test （BIST）. By all means above, the result shows that the fault coverage may reach 97%, and the SoC chip is implemented successfully by using 0.25 μm two-poly four-metal mixed signal complementary metal oxide semiconductor （CMOS） technology, the die area is 4.8×4.6 mm^2. Test results show that the maximum throughput of Ethemet packets may reach 7Mb·s^1.

An LFSR-based address generator using optimized address partition for low power memory BIST

Power consumption in test mode is much higher than that in normal mode,which is prone to causing circuit damage and reducing the yield of chips.To reduce the power dissipation efficiently,a modified linear feedback shift register(LFSR)is designed to decrease switching activity dramatically during the generation of address sequences for memory built-in self-test(MBIST).The address models are generated by a blend of two address generators with an optimized address partition and two distinct controlled clock signals.An address generator circuit for MBIST of 64 k×32 static random access memory(SRAM)is designed to illustrate the proposed scheme.Experimental results show that when the address bus size is 16 bits,compared with the traditional LFSR,the proposed LFSR can reduce the switching activity and dynamic power by 71.1%and 68.2%,respectively,with low area overhead.

Comparative analysis between chaotic sequence and PN sequence in spread spectrum system

This paper introduces two kinds of sequences used in spread spectrum communication system： pseudo-noise （PN） se-quence generated by linear feedback shift register（LFSR）, such as m-sequence and Gold sequence, and the chaotic sequence generated by the determination of the nonlinear system. The characteristics of PN sequence and chaotic sequence are analyzed by simulation, and the advantages and disadvantages of different sequences in spread spectrum communication system are ob-tained. The advantages of sequence can be used to improve signal transmission in a spread spectrum communication system.

Low Cost BIST Scheme Using LFSR-RC Reseeding

A novel BIST scheme for reducing the test storage( TS) is presented. The proposed approach relies on a two-dimensional compression scheme,which combines the advantages of the previous LFSR reseeding scheme and test set embedding technique based on ring counters( RCs) to improve the encoding efficiency. It presents a general method to determine the probability of encoding as a function of the number of specified bits in the test cube,the length of the LFSR and the width of the test set,and conclude that the probability of encoding a n-bit test cube with s specified bits using a( smax+ 1 + 20 / n)-stage LFSR with a fixed polynomial is1- 10-6. Experimental results for the ISCAS '89 benchmark circuits show that compared with the previous schemes,the proposed scheme based on LFSR-RC reseeding requires 57% less TS and 99. 1% test application time( TAT) with simple and uniform BIST control logic.

Scan-Based Attack on Stream Ciphers: A Case Study on eSTREAM Finalists

Scan-based design for test （DFT） is a powerful and the most popular testing technique. However, while scan-based DFT improves test efficiency, it also leaves a side channel to the privacy information stored in the chip. This paper investigates the side channel and proposes a simple but powerful scan-based attack that can reveal the key and/or state stored in the chips that implement the state-of-the-art stream ciphers with less than 85 scan-out vectors.