1 Multiple-β transistor and linear AND-OR gate The high-speed and real-time processing of information requires a higher and higher operating speed for digital-integrated circuits. Making efforts to exploit silicon-in...1 Multiple-β transistor and linear AND-OR gate The high-speed and real-time processing of information requires a higher and higher operating speed for digital-integrated circuits. Making efforts to exploit silicon-integrated circuits with high speed, scientists pay attention to the bipolar-integrated circuits.展开更多
By using comparison operations, three basic operations, AND, OR and NOT, in Boolean algebra are re-defined Based on the characteristic that the voltage signals are easy to implement comparison operation, various logic...By using comparison operations, three basic operations, AND, OR and NOT, in Boolean algebra are re-defined Based on the characteristic that the voltage signals are easy to implement comparison operation, various logic functions realized by connecting emitters of the bipolar transistor are analyzed. Furthermore, a novel multiple-β transistor and the linear AND-OR gate, which is composed of the transistor, are investigated. Super high-speed characteristic and multiple-cascade capability of the linear AND-OR gate are verified by PSPICE simulation. Based on the analysis of high-speed switch, which is compatible with the linear AND-OR gate, a high-speed inverter is proposed, which is composed of multiple-β transistors. The corresponding flip-flop design is also given. Finally, the criterion for using linear AND-OR gate to design high-speed switching circuits are presented. Some combinational and sequential circuits are designed as the practical examples. Discussion indicates that the switching circuits based on multiple-β transistor can be applied in high-speed design field.展开更多
随着晶体管尺寸按比例缩小,越来越薄的氧化层厚度导致栅上的隧穿电流显著地增大,严重地影响器件和电路的静态特性,为此,基于可靠性理论和仿真,对小尺寸MOSFET(metal-oxide-semiconductor field effect transistor)的直接隧穿栅电流进行...随着晶体管尺寸按比例缩小,越来越薄的氧化层厚度导致栅上的隧穿电流显著地增大,严重地影响器件和电路的静态特性,为此,基于可靠性理论和仿真,对小尺寸MOSFET(metal-oxide-semiconductor field effect transistor)的直接隧穿栅电流进行研究,并通过对二输入或非门静态栅泄漏电流的研究,揭示直接隧穿栅电流对CMOS(complementary metal oxide semiconductor)逻辑电路的影响。仿真工具为HSPICE软件,MOS器件模型参数采用的是BSIM4和LEVEL 54,栅氧化层厚度为1.4 nm。研究结果表明:边缘直接隧穿电流是小尺寸MOS器件栅直接隧穿电流的重要组成成分;漏端偏置和衬底偏置通过改变表面势影响栅电流密度;CMOS逻辑电路中MOS器件有4种工作状态,即线性区、饱和区、亚阈区和截止区;CMOS逻辑电路中MOS器件的栅泄漏电流与其工作状态有关。仿真结果与理论分析结果较符合,这些理论和仿真结果有助于以后的集成电路设计。展开更多
通过对碳纳米场效应晶体管(Carbon Nanotube Field Effect Transistor,CNFET)的研究,提出一种基于CNFET的低功耗三值门电路设计方案.该方案在分析CNFET结构及其不同尺寸的碳纳米管对应于不同阈值电压特性的基础上,以多值逻辑理论为指导...通过对碳纳米场效应晶体管(Carbon Nanotube Field Effect Transistor,CNFET)的研究,提出一种基于CNFET的低功耗三值门电路设计方案.该方案在分析CNFET结构及其不同尺寸的碳纳米管对应于不同阈值电压特性的基础上,以多值逻辑理论为指导,设计基于CNFET的三值反相器、与非门、或非门等单元门电路,最后利用HSPICE对所设计的电路进行仿真.结果表明:所设计电路具有正确的逻辑功能,与传统三值门电路相比,三值CNFET门电路平均传输速度提高52.7%,平均能耗节省54.9%.展开更多
文摘1 Multiple-β transistor and linear AND-OR gate The high-speed and real-time processing of information requires a higher and higher operating speed for digital-integrated circuits. Making efforts to exploit silicon-integrated circuits with high speed, scientists pay attention to the bipolar-integrated circuits.
基金Project supported by the National Natural Science Foundation of China.
文摘By using comparison operations, three basic operations, AND, OR and NOT, in Boolean algebra are re-defined Based on the characteristic that the voltage signals are easy to implement comparison operation, various logic functions realized by connecting emitters of the bipolar transistor are analyzed. Furthermore, a novel multiple-β transistor and the linear AND-OR gate, which is composed of the transistor, are investigated. Super high-speed characteristic and multiple-cascade capability of the linear AND-OR gate are verified by PSPICE simulation. Based on the analysis of high-speed switch, which is compatible with the linear AND-OR gate, a high-speed inverter is proposed, which is composed of multiple-β transistors. The corresponding flip-flop design is also given. Finally, the criterion for using linear AND-OR gate to design high-speed switching circuits are presented. Some combinational and sequential circuits are designed as the practical examples. Discussion indicates that the switching circuits based on multiple-β transistor can be applied in high-speed design field.
文摘随着晶体管尺寸按比例缩小,越来越薄的氧化层厚度导致栅上的隧穿电流显著地增大,严重地影响器件和电路的静态特性,为此,基于可靠性理论和仿真,对小尺寸MOSFET(metal-oxide-semiconductor field effect transistor)的直接隧穿栅电流进行研究,并通过对二输入或非门静态栅泄漏电流的研究,揭示直接隧穿栅电流对CMOS(complementary metal oxide semiconductor)逻辑电路的影响。仿真工具为HSPICE软件,MOS器件模型参数采用的是BSIM4和LEVEL 54,栅氧化层厚度为1.4 nm。研究结果表明:边缘直接隧穿电流是小尺寸MOS器件栅直接隧穿电流的重要组成成分;漏端偏置和衬底偏置通过改变表面势影响栅电流密度;CMOS逻辑电路中MOS器件有4种工作状态,即线性区、饱和区、亚阈区和截止区;CMOS逻辑电路中MOS器件的栅泄漏电流与其工作状态有关。仿真结果与理论分析结果较符合,这些理论和仿真结果有助于以后的集成电路设计。
文摘通过对碳纳米场效应晶体管(Carbon Nanotube Field Effect Transistor,CNFET)的研究,提出一种基于CNFET的低功耗三值门电路设计方案.该方案在分析CNFET结构及其不同尺寸的碳纳米管对应于不同阈值电压特性的基础上,以多值逻辑理论为指导,设计基于CNFET的三值反相器、与非门、或非门等单元门电路,最后利用HSPICE对所设计的电路进行仿真.结果表明:所设计电路具有正确的逻辑功能,与传统三值门电路相比,三值CNFET门电路平均传输速度提高52.7%,平均能耗节省54.9%.
