DAG-MAP is an FPGA technology mapping algorithm for delay optimization and the labeling phase is the algorithm’s kernel. This paper studied the labeling phase and presented an improved labeling method. It is shown th...DAG-MAP is an FPGA technology mapping algorithm for delay optimization and the labeling phase is the algorithm’s kernel. This paper studied the labeling phase and presented an improved labeling method. It is shown through the experimental results on MCNC benchmarks that the improved method is more effective than the original method while the computation time is almost the same.展开更多
Reed-Muller logic is becoming increasingly attractive. However, its synthesis and optimization are difficult especially for mixed polarity Reed-Muller logic. In this paper, a function is expressed into a truth vector....Reed-Muller logic is becoming increasingly attractive. However, its synthesis and optimization are difficult especially for mixed polarity Reed-Muller logic. In this paper, a function is expressed into a truth vector. Product shrinkage, general sum shrinkage （GSS）, elimination and extraction operators are proposed to shrink the truth vector. A novel algorithm is presented to derive a compact Multi-level Mixed Polarity Reed-Muller Form （MMPRMF） starting from a given fixed polarity truth vector. The results show that a significant area improvement can be made compared with published results.展开更多
文摘DAG-MAP is an FPGA technology mapping algorithm for delay optimization and the labeling phase is the algorithm’s kernel. This paper studied the labeling phase and presented an improved labeling method. It is shown through the experimental results on MCNC benchmarks that the improved method is more effective than the original method while the computation time is almost the same.
文摘Reed-Muller logic is becoming increasingly attractive. However, its synthesis and optimization are difficult especially for mixed polarity Reed-Muller logic. In this paper, a function is expressed into a truth vector. Product shrinkage, general sum shrinkage （GSS）, elimination and extraction operators are proposed to shrink the truth vector. A novel algorithm is presented to derive a compact Multi-level Mixed Polarity Reed-Muller Form （MMPRMF） starting from a given fixed polarity truth vector. The results show that a significant area improvement can be made compared with published results.
