Energy Recovery Capacitance Coupling Logic and Its Synthesis Methodology

A novel energy recovery logic style ERCCL （energy recovery capacitance coupling logic） , which has good energy performance compared to the conventional CMOS logic and other advanced energy recovery logic, is proposed. ERCCL uses capacitance coupling to perform a logic function, so it can energy-efficiently implement a high fan-in complex logic in a single gate. ERCCL is also a type of threshold logic. The gate count of a system based on ERCCL can be significantly reduced,which,in turn,will decrease the energy loss. A threshold logic synthesis methodology for ERCCL is also presented. MCNC benchmarks are run through the proposed synthesis methodology. The results indicate that about an 80% reduction in gate count can be obtained when compared with the synthesis results of SIS.

A General Method in the Synthesis of Ternary Double Pass-Transistor Circuits

A general method for designing ternary circuits using double pass-transistor logic is investigated. The logical relation of each MOS transistor is formulated by using the transmission operation in order to make effective and practical use of the circuits. A way to generate ternary complementary and dual circuits by applying the complementarity and duality principles is presented. This new static ternary double pass-transistor logic scheme has some favorable properties：the use of standard CMOS process without any modification of the thresholds, a perfectly symmetrical structure,a full logic swing, the maximum possible noise margins, a less complex structure, and no static power consumption. HSPICE simulations using TSMC 0.25μm CMOS technology and a 3V power supply demonstrate the effectiveness of the proposed design.

POWER OPTIMIZATION ALGORITHM BASED ON XNOR/OR LOGIC

Based on the investigation of the XNOR/OR logical expression and the propagation al- gorithm of signal probability, a low power synthesis algorithm based on the XNOR/OR logic is pro- posed in this paper. The proposed algorithm has been implemented with C language. Fourteen Mi- croelectronics Center North Carolina (MCNC) benchmarks are tested, and the results show that the proposed algorithm not only significantly reduces the average power consumption up to 27% without area and delay compensations, but also makes the runtime shorter.

DYNAMIC LABELING BASED FPGA DELAY OPTIMIZATION ALGORITHM

DAG-MAP is an FPGA technology mapping algorithm for delay optimization and the labeling phase is the algorithm’s kernel. This paper studied the labeling phase and presented an improved labeling method. It is shown through the experimental results on MCNC benchmarks that the improved method is more effective than the original method while the computation time is almost the same.

Novel Synthesis and Optimization of Multi-Level Mixed Polarity Reed-Muller Functions

Reed-Muller logic is becoming increasingly attractive. However, its synthesis and optimization are difficult especially for mixed polarity Reed-Muller logic. In this paper, a function is expressed into a truth vector. Product shrinkage, general sum shrinkage （GSS）, elimination and extraction operators are proposed to shrink the truth vector. A novel algorithm is presented to derive a compact Multi-level Mixed Polarity Reed-Muller Form （MMPRMF） starting from a given fixed polarity truth vector. The results show that a significant area improvement can be made compared with published results.