In scaled CMOS processes, the single-event effects generate missing output pulses in Delay-Locked Loop (DLL). Due to its effective sequence detection of the missing pulses in the proposed Error Correction Circuit (ECC...In scaled CMOS processes, the single-event effects generate missing output pulses in Delay-Locked Loop (DLL). Due to its effective sequence detection of the missing pulses in the proposed Error Correction Circuit (ECC) and its portability to be applied to any DLL type, the ECC mitigates the impact of single-event effects and completes its operation with less design complexity without any concern about losing the information. The ECC has been implemented in 180 nm CMOS process and measured the accuracy of mitigation on simulations at LETs up to 100 MeV-cm<sup>2</sup>/mg. The robustness and portability of the mitigation technique are validated through the results obtained by implementing proposed ECC in XilinxArtix 7 FPGA.展开更多
The equivalent circuit of single-cavity multiple-device fundamentaloscillator(SCMDFO)and that of single-device harmonic oscillator(SDHO)proposed byK.Kurokawa and K.Solbach,respectively,are extended and applied to a si...The equivalent circuit of single-cavity multiple-device fundamentaloscillator(SCMDFO)and that of single-device harmonic oscillator(SDHO)proposed byK.Kurokawa and K.Solbach,respectively,are extended and applied to a single-cavitymultiple-device harmonic oscillator(SCMDHO).By means of describing the functions ofnonlinearity of Gunn diodes,the performances of the SCMDHO are analyzed.It is foundthat the voltage amplitudes are similar to those of SDHO,and the ratio of maximum pow-er of harmonic to that of fundamental is identical to that in SDHO when the devices havesame parameters.The harmonic injection locking behavior is also investigated.The injec-tion locking range is greater than that of SDHO if locking gain remains constant.A2-Gunn diode harmonic oscillator was designed.It delivers 30mW output power at103GHz.The mechanical tuning range is 4.15GHz when the output power remains morethan 10mW.The desired operation mode is stable.展开更多
A new reliability-based multidisciplinary design optimization （RBMDO） framework is proposed by combining the single-loop-based reliability analysis （SLBRA） method with multidisciplinary feasible （MDF） method. Th...A new reliability-based multidisciplinary design optimization （RBMDO） framework is proposed by combining the single-loop-based reliability analysis （SLBRA） method with multidisciplinary feasible （MDF） method. The Kriging approximate model with updating is introduced to reduce the computational cost of MDF caused by the complex structure. The computational efficiency is remarkably improved as the lack of iterative process during reliability analysis. Special attention is paid to a turbine blade design optimization by adopting the proposed method. Results show that the method is much more efficient than the commonly used double-loop based RBMDO method. It is feasible and efficient to apply the method to the engineering design.展开更多
在宁夏的中东部地区,风光资源良好,大量光伏电站以及风电场并入大电网,促进风光资源的有效利用与开发。随着新型光伏材料的出现,成本不断降低,转换效率不断提高,光伏并网得到大量推广。为实现光伏并网逆变器的快速并网,针对单级式光伏...在宁夏的中东部地区,风光资源良好,大量光伏电站以及风电场并入大电网,促进风光资源的有效利用与开发。随着新型光伏材料的出现,成本不断降低,转换效率不断提高,光伏并网得到大量推广。为实现光伏并网逆变器的快速并网,针对单级式光伏并网逆变器锁相环进行研究,分析传统的锁相环因存在1/4周期的延迟,导致跟踪性及动态响应不佳,提出了基于二阶广义积分器(Second Order Generalized Integrator,SOGI)的锁相环并进行对比分析,将SOGI引入后,提高了并网逆变器的并网效率和动态响应,对于光伏并网逆变系统具有一定的研究意义。展开更多
A radiation-hardened-by-design phase-locked loop（PLL） with a frequency range of 200 to 1000 MHz is proposed.By presenting a novel charge compensation circuit,composed by a lock detector circuit,two operational ampli...A radiation-hardened-by-design phase-locked loop（PLL） with a frequency range of 200 to 1000 MHz is proposed.By presenting a novel charge compensation circuit,composed by a lock detector circuit,two operational amplifiers,and four MOS devices,the proposed PLL significantly reduces the recovery time after the presence of a single event transient（SET）.Comparing with many traditional hardened methods,most of which endeavor to enhance the immunity of the charge pump output node to an SET,the novel PLL can also decrease its susceptibility in the presence of an SET in other blocks.A novel system model is presented to describe immunity of a PLL to an SET and used to compare the sensitivity of traditional and hardened PLLs to an SET.An SET is simulated on Sentaurus TCAD simulation workbench to model the induced pulse current.Post simulation with a 130 nm CMOS process model shows that the recovery time of the proposed PLL reduces by up to 93.5%compared with the traditional one,at the same time,the charge compensation circuit adds no complexity to the systemic parameter design.展开更多
文摘In scaled CMOS processes, the single-event effects generate missing output pulses in Delay-Locked Loop (DLL). Due to its effective sequence detection of the missing pulses in the proposed Error Correction Circuit (ECC) and its portability to be applied to any DLL type, the ECC mitigates the impact of single-event effects and completes its operation with less design complexity without any concern about losing the information. The ECC has been implemented in 180 nm CMOS process and measured the accuracy of mitigation on simulations at LETs up to 100 MeV-cm<sup>2</sup>/mg. The robustness and portability of the mitigation technique are validated through the results obtained by implementing proposed ECC in XilinxArtix 7 FPGA.
基金The Project Supported by National Science Foundation of China
文摘The equivalent circuit of single-cavity multiple-device fundamentaloscillator(SCMDFO)and that of single-device harmonic oscillator(SDHO)proposed byK.Kurokawa and K.Solbach,respectively,are extended and applied to a single-cavitymultiple-device harmonic oscillator(SCMDHO).By means of describing the functions ofnonlinearity of Gunn diodes,the performances of the SCMDHO are analyzed.It is foundthat the voltage amplitudes are similar to those of SDHO,and the ratio of maximum pow-er of harmonic to that of fundamental is identical to that in SDHO when the devices havesame parameters.The harmonic injection locking behavior is also investigated.The injec-tion locking range is greater than that of SDHO if locking gain remains constant.A2-Gunn diode harmonic oscillator was designed.It delivers 30mW output power at103GHz.The mechanical tuning range is 4.15GHz when the output power remains morethan 10mW.The desired operation mode is stable.
基金Supported by the National High Technology Research and Development Program of China("863" Program) (2009AA04Z418, 2007AA04Z404)the National "111" Project(B07050)~~
文摘A new reliability-based multidisciplinary design optimization （RBMDO） framework is proposed by combining the single-loop-based reliability analysis （SLBRA） method with multidisciplinary feasible （MDF） method. The Kriging approximate model with updating is introduced to reduce the computational cost of MDF caused by the complex structure. The computational efficiency is remarkably improved as the lack of iterative process during reliability analysis. Special attention is paid to a turbine blade design optimization by adopting the proposed method. Results show that the method is much more efficient than the commonly used double-loop based RBMDO method. It is feasible and efficient to apply the method to the engineering design.
文摘在宁夏的中东部地区,风光资源良好,大量光伏电站以及风电场并入大电网,促进风光资源的有效利用与开发。随着新型光伏材料的出现,成本不断降低,转换效率不断提高,光伏并网得到大量推广。为实现光伏并网逆变器的快速并网,针对单级式光伏并网逆变器锁相环进行研究,分析传统的锁相环因存在1/4周期的延迟,导致跟踪性及动态响应不佳,提出了基于二阶广义积分器(Second Order Generalized Integrator,SOGI)的锁相环并进行对比分析,将SOGI引入后,提高了并网逆变器的并网效率和动态响应,对于光伏并网逆变系统具有一定的研究意义。
基金supported by the National Defense Pre-Research Project of China(No.51308010610)
文摘A radiation-hardened-by-design phase-locked loop（PLL） with a frequency range of 200 to 1000 MHz is proposed.By presenting a novel charge compensation circuit,composed by a lock detector circuit,two operational amplifiers,and four MOS devices,the proposed PLL significantly reduces the recovery time after the presence of a single event transient（SET）.Comparing with many traditional hardened methods,most of which endeavor to enhance the immunity of the charge pump output node to an SET,the novel PLL can also decrease its susceptibility in the presence of an SET in other blocks.A novel system model is presented to describe immunity of a PLL to an SET and used to compare the sensitivity of traditional and hardened PLLs to an SET.An SET is simulated on Sentaurus TCAD simulation workbench to model the induced pulse current.Post simulation with a 130 nm CMOS process model shows that the recovery time of the proposed PLL reduces by up to 93.5%compared with the traditional one,at the same time,the charge compensation circuit adds no complexity to the systemic parameter design.
